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authorDavid Woodhouse <David.Woodhouse@intel.com>2008-07-25 10:40:14 -0400
committerDavid Woodhouse <David.Woodhouse@intel.com>2008-07-25 10:40:14 -0400
commitff877ea80efa2015b6263766f78ee42c2a1b32f9 (patch)
tree85205005c611ab774702148558321c6fb92f1ccd /arch/arm/mach-at91/board-yl-9200.c
parent30821fee4f0cb3e6d241d9f7ddc37742212e3eb7 (diff)
parentd37e6bf68fc1eb34a4ad21d9ae8890ed37ea80e7 (diff)
Merge branch 'linux-next' of git://git.infradead.org/~dedekind/ubi-2.6
Diffstat (limited to 'arch/arm/mach-at91/board-yl-9200.c')
-rwxr-xr-xarch/arm/mach-at91/board-yl-9200.c853
1 files changed, 387 insertions, 466 deletions
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index e642b3a8bd10..bbbfd06f5e0c 100755
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -1,11 +1,10 @@
1/* 1/*
2 * linux/arch/arm/mach-at91/board-yl-9200.c 2 * linux/arch/arm/mach-at91/board-yl-9200.c
3 * 3 *
4 * Adapted from: 4 * Adapted from various board files in arch/arm/mach-at91
5 *various board files in 5 *
6 * /arch/arm/mach-at91 6 * Modifications for YL-9200 platform:
7 * modifications to convert to YL-9200 platform 7 * Copyright (C) 2007 S. Birtles
8 * Copyright (C) 2007 S.Birtles
9 * 8 *
10 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by 10 * it under the terms of the GNU General Public License as published by
@@ -26,13 +25,14 @@
26#include <linux/init.h> 25#include <linux/init.h>
27#include <linux/mm.h> 26#include <linux/mm.h>
28#include <linux/module.h> 27#include <linux/module.h>
28#include <linux/dma-mapping.h>
29#include <linux/platform_device.h> 29#include <linux/platform_device.h>
30#include <linux/spi/spi.h> 30#include <linux/spi/spi.h>
31/*#include <linux/can_bus/candata.h>*/
32#include <linux/spi/ads7846.h> 31#include <linux/spi/ads7846.h>
33#include <linux/mtd/physmap.h> 32#include <linux/mtd/physmap.h>
33#include <linux/gpio_keys.h>
34#include <linux/input.h>
34 35
35/*#include <sound/gpio_sounder.h>*/
36#include <asm/hardware.h> 36#include <asm/hardware.h>
37#include <asm/setup.h> 37#include <asm/setup.h>
38#include <asm/mach-types.h> 38#include <asm/mach-types.h>
@@ -45,179 +45,108 @@
45#include <asm/arch/board.h> 45#include <asm/arch/board.h>
46#include <asm/arch/gpio.h> 46#include <asm/arch/gpio.h>
47#include <asm/arch/at91rm9200_mc.h> 47#include <asm/arch/at91rm9200_mc.h>
48#include <linux/gpio_keys.h>
49#include <linux/input.h>
50 48
51#include "generic.h" 49#include "generic.h"
52#include <asm/arch/at91_pio.h>
53 50
54#define YL_9200_FLASH_BASE AT91_CHIPSELECT_0
55#define YL_9200_FLASH_SIZE 0x800000
56 51
57/* 52static void __init yl9200_map_io(void)
58 * Serial port configuration. 53{
59 * 0 .. 3 = USART0 .. USART3 54 /* Initialize processor: 18.432 MHz crystal */
60 * 4 = DBGU 55 at91rm9200_initialize(18432000, AT91RM9200_PQFP);
61 *atmel_usart.0: ttyS0 at MMIO 0xfefff200 (irq = 1) is a ATMEL_SERIAL
62 *atmel_usart.1: ttyS1 at MMIO 0xfffc0000 (irq = 6) is a ATMEL_SERIAL
63 *atmel_usart.2: ttyS2 at MMIO 0xfffc4000 (irq = 7) is a ATMEL_SERIAL
64 *atmel_usart.3: ttyS3 at MMIO 0xfffc8000 (irq = 8) is a ATMEL_SERIAL
65 *atmel_usart.4: ttyS4 at MMIO 0xfffcc000 (irq = 9) is a ATMEL_SERIAL
66 * on the YL-9200 we are sitting at the following
67 *ttyS0 at MMIO 0xfefff200 (irq = 1) is a AT91_SERIAL
68 *ttyS1 at MMIO 0xfefc4000 (irq = 7) is a AT91_SERIAL
69 */
70 56
71/* extern void __init yl_9200_add_device_sounder(struct gpio_sounder *sounders, int nr);*/ 57 /* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */
58 at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17);
72 59
73static struct at91_uart_config __initdata yl_9200_uart_config = { 60 /* DBGU on ttyS0. (Rx & Tx only) */
74 .console_tty = 0, /* ttyS0 */ 61 at91_register_uart(0, 0, 0);
75 .nr_tty = 3,
76 .tty_map = { 4, 1, 0, -1, -1 } /* ttyS0, ..., ttyS4 */
77};
78 62
79static void __init yl_9200_map_io(void) 63 /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
80{ 64 at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
81 /* Initialize processor: 18.432 MHz crystal */ 65 | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
82 /*Also initialises register clocks & gpio*/ 66 | ATMEL_UART_RI);
83 at91rm9200_initialize(18432000, AT91RM9200_PQFP); /*we have a 3 bank system*/
84 67
85 /* Setup the serial ports and console */ 68 /* USART0 on ttyS2. (Rx & Tx only to JP3) */
86 at91_init_serial(&yl_9200_uart_config); 69 at91_register_uart(AT91RM9200_ID_US0, 2, 0);
87 70
88 /* Setup the LEDs D2=PB17,D3=PB16 */ 71 /* USART3 on ttyS3. (Rx, Tx, RTS - RS485 interface) */
89 at91_init_leds(AT91_PIN_PB16,AT91_PIN_PB17); /*cpu-led,timer-led*/ 72 at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_RTS);
73
74 /* set serial console to ttyS0 (ie, DBGU) */
75 at91_set_serial_console(0);
90} 76}
91 77
92static void __init yl_9200_init_irq(void) 78static void __init yl9200_init_irq(void)
93{ 79{
94 at91rm9200_init_interrupts(NULL); 80 at91rm9200_init_interrupts(NULL);
95} 81}
96 82
97static struct at91_eth_data __initdata yl_9200_eth_data = {
98 .phy_irq_pin = AT91_PIN_PB28,
99 .is_rmii = 1,
100};
101 83
102static struct at91_usbh_data __initdata yl_9200_usbh_data = { 84/*
103 .ports = 1, /* this should be 1 not 2 for the Yl9200*/ 85 * LEDs
86 */
87static struct gpio_led yl9200_leds[] = {
88 { /* D2 */
89 .name = "led2",
90 .gpio = AT91_PIN_PB17,
91 .active_low = 1,
92 .default_trigger = "timer",
93 },
94 { /* D3 */
95 .name = "led3",
96 .gpio = AT91_PIN_PB16,
97 .active_low = 1,
98 .default_trigger = "heartbeat",
99 },
100 { /* D4 */
101 .name = "led4",
102 .gpio = AT91_PIN_PB15,
103 .active_low = 1,
104 },
105 { /* D5 */
106 .name = "led5",
107 .gpio = AT91_PIN_PB8,
108 .active_low = 1,
109 }
104}; 110};
105 111
106static struct at91_udc_data __initdata yl_9200_udc_data = {
107/*on sheet 7 Schemitic rev 1.0*/
108 .pullup_pin = AT91_PIN_PC4,
109 .vbus_pin= AT91_PIN_PC5,
110 .pullup_active_low = 1, /*ACTIVE LOW!! due to PNP transistor on page 7*/
111
112};
113/* 112/*
114static struct at91_cf_data __initdata yl_9200_cf_data = { 113 * Ethernet
115TODO S.BIRTLES 114 */
116 .det_pin = AT91_PIN_xxx, 115static struct at91_eth_data __initdata yl9200_eth_data = {
117 .rst_pin = AT91_PIN_xxx, 116 .phy_irq_pin = AT91_PIN_PB28,
118 .irq_pin = ... not connected 117 .is_rmii = 1,
119 .vcc_pin = ... always powered
120
121}; 118};
122*/
123static struct at91_mmc_data __initdata yl_9200_mmc_data = {
124 .det_pin = AT91_PIN_PB9, /*THIS LOOKS CORRECT SHEET7*/
125/* .wp_pin = ... not connected SHEET7*/
126 .slot_b = 0,
127 .wire4 = 1,
128 119
120/*
121 * USB Host
122 */
123static struct at91_usbh_data __initdata yl9200_usbh_data = {
124 .ports = 1, /* PQFP version of AT91RM9200 */
129}; 125};
130 126
131/* -------------------------------------------------------------------- 127/*
132 * Touch screen 128 * USB Device
133 * -------------------------------------------------------------------- */ 129 */
134#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) 130static struct at91_udc_data __initdata yl9200_udc_data = {
135static int ads7843_pendown_state(void) 131 .pullup_pin = AT91_PIN_PC4,
136{ 132 .vbus_pin = AT91_PIN_PC5,
137 return !at91_get_gpio_value(AT91_PIN_PB11); /* Touchscreen PENIRQ */ 133 .pullup_active_low = 1, /* Active Low due to PNP transistor (pg 7) */
138}
139
140static void __init at91_init_device_ts(void)
141{
142/*IMPORTANT NOTE THE SPI INTERFACE IS ALREADY CONFIGURED BY XXX_DEVICES.C
143THAT IS TO SAY THAT MISO,MOSI,SPCK AND CS are already configured
144we only need to enable the other datapins which are:
145PB10/RK1 BUSY
146*/
147/* Touchscreen BUSY signal , pin,use pullup ( TODO not currently used in the ADS7843/6.c driver)*/
148at91_set_gpio_input(AT91_PIN_PB10, 1);
149}
150
151#else
152static void __init at91_init_device_ts(void) {}
153#endif
154
155static struct ads7846_platform_data ads_info = {
156 .model = 7843,
157 .x_min = 150,
158 .x_max = 3830,
159 .y_min = 190,
160 .y_max = 3830,
161 .vref_delay_usecs = 100,
162/* for a 8" touch screen*/
163 //.x_plate_ohms = 603, //= 450, S.Birtles TODO
164 //.y_plate_ohms = 332, //= 250, S.Birtles TODO
165/*for a 10.4" touch screen*/
166 //.x_plate_ohms =611,
167 //.y_plate_ohms =325,
168
169 .x_plate_ohms = 576,
170 .y_plate_ohms = 366,
171 //
172 .pressure_max = 15000, /*generally nonsense on the 7843*/
173 /*number of times to send query to chip in a given run 0 equals one time (do not set to 0!! ,there is a bug in ADS 7846 code)*/
174 .debounce_max = 1,
175 .debounce_rep = 0,
176 .debounce_tol = (~0),
177 .get_pendown_state = ads7843_pendown_state,
178};
179 134
180/*static struct canbus_platform_data can_info = {
181 .model = 2510,
182}; 135};
183*/
184
185static struct spi_board_info yl_9200_spi_devices[] = {
186/*this sticks it at:
187 /sys/devices/platform/atmel_spi.0/spi0.0
188 /sys/bus/platform/devices/
189Documentation/spi IIRC*/
190 136
191#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) 137/*
192 /*(this IS correct 04-NOV-2007)*/ 138 * MMC
193 { 139 */
194 .modalias = "ads7846", /* because the driver is called ads7846*/ 140static struct at91_mmc_data __initdata yl9200_mmc_data = {
195 .chip_select = 0, /*THIS MUST BE AN INDEX INTO AN ARRAY OF pins */ 141 .det_pin = AT91_PIN_PB9,
196/*this is ONLY TO BE USED if chipselect above is not used, it passes a pin directly for the chip select*/ 142 // .wp_pin = ... not connected
197 /*.controller_data =AT91_PIN_PA3 ,*/ 143 .wire4 = 1,
198 .max_speed_hz = 5000*26, /*(4700 * 26)-125000 * 26, (max sample rate @ 3V) * (cmd + data + overhead) */
199 .bus_num = 0,
200 .platform_data = &ads_info,
201 .irq = AT91_PIN_PB11,
202 },
203#endif
204/*we need to put our CAN driver data here!!*/
205/*THIS IS ALL DUMMY DATA*/
206/* {
207 .modalias = "mcp2510", //DUMMY for MCP2510 chip
208 .chip_select = 1,*/ /*THIS MUST BE AN INDEX INTO AN ARRAY OF pins */
209 /*this is ONLY TO BE USED if chipselect above is not used, it passes a pin directly for the chip select */
210 /* .controller_data =AT91_PIN_PA4 ,
211 .max_speed_hz = 25000 * 26,
212 .bus_num = 0,
213 .platform_data = &can_info,
214 .irq = AT91_PIN_PC0,
215 },
216 */
217 //max SPI chip needs to go here
218}; 144};
219 145
220static struct mtd_partition __initdata yl_9200_nand_partition[] = { 146/*
147 * NAND Flash
148 */
149static struct mtd_partition __initdata yl9200_nand_partition[] = {
221 { 150 {
222 .name = "AT91 NAND partition 1, boot", 151 .name = "AT91 NAND partition 1, boot",
223 .offset = 0, 152 .offset = 0,
@@ -242,442 +171,434 @@ static struct mtd_partition __initdata yl_9200_nand_partition[] = {
242 .name = "AT91 NAND partition 5, ext-fs", 171 .name = "AT91 NAND partition 5, ext-fs",
243 .offset = 32 * SZ_1M, 172 .offset = 32 * SZ_1M,
244 .size = 32 * SZ_1M 173 .size = 32 * SZ_1M
245 }, 174 }
246}; 175};
247 176
248static struct mtd_partition * __init nand_partitions(int size, int *num_partitions) 177static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
249{ 178{
250 *num_partitions = ARRAY_SIZE(yl_9200_nand_partition); 179 *num_partitions = ARRAY_SIZE(yl9200_nand_partition);
251 return yl_9200_nand_partition; 180 return yl9200_nand_partition;
252} 181}
253 182
254static struct atmel_nand_data __initdata yl_9200_nand_data = { 183static struct atmel_nand_data __initdata yl9200_nand_data = {
255 .ale= 6, 184 .ale = 6,
256 .cle= 7, 185 .cle = 7,
257 /*.det_pin = AT91_PIN_PCxx,*/ /*we don't have a det pin because NandFlash is fixed to board*/ 186 // .det_pin = ... not connected
258 .rdy_pin = AT91_PIN_PC14, /*R/!B Sheet10*/ 187 .rdy_pin = AT91_PIN_PC14, /* R/!B (Sheet10) */
259 .enable_pin = AT91_PIN_PC15, /*!CE Sheet10 */ 188 .enable_pin = AT91_PIN_PC15, /* !CE (Sheet10) */
260 .partition_info = nand_partitions, 189 .partition_info = nand_partitions,
261}; 190};
262 191
263
264
265/* 192/*
266TODO S.Birtles 193 * NOR Flash
267potentially a problem with the size above 194 */
268physmap platform flash device: 00800000 at 10000000 195#define YL9200_FLASH_BASE AT91_CHIPSELECT_0
269physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank 196#define YL9200_FLASH_SIZE 0x1000000
270NOR chip too large to fit in mapping. Attempting to cope...
271 Intel/Sharp Extended Query Table at 0x0031
272Using buffer write method
273cfi_cmdset_0001: Erase suspend on write enabled
274Reducing visibility of 16384KiB chip to 8192KiB
275*/
276 197
277static struct mtd_partition yl_9200_flash_partitions[] = { 198static struct mtd_partition yl9200_flash_partitions[] = {
199 {
200 .name = "Bootloader",
201 .size = 0x00040000,
202 .offset = 0,
203 .mask_flags = MTD_WRITEABLE, /* force read-only */
204 },
278 { 205 {
279 .name = "Bootloader", 206 .name = "Kernel",
280 .size = 0x00040000, 207 .size = 0x001C0000,
281 .offset = 0, 208 .offset = 0x00040000,
282 .mask_flags = MTD_WRITEABLE /* force read-only */ 209 },
283 },{ 210 {
284 .name = "Kernel", 211 .name = "Filesystem",
285 .size = 0x001C0000, 212 .size = MTDPART_SIZ_FULL,
286 .offset = 0x00040000, 213 .offset = 0x00200000
287 },{
288 .name = "Filesystem",
289 .size = MTDPART_SIZ_FULL,
290 .offset = 0x00200000
291 } 214 }
292
293}; 215};
294 216
295static struct physmap_flash_data yl_9200_flash_data = { 217static struct physmap_flash_data yl9200_flash_data = {
296 .width = 2, 218 .width = 2,
297 .parts = yl_9200_flash_partitions, 219 .parts = yl9200_flash_partitions,
298 .nr_parts = ARRAY_SIZE(yl_9200_flash_partitions), 220 .nr_parts = ARRAY_SIZE(yl9200_flash_partitions),
299}; 221};
300 222
301static struct resource yl_9200_flash_resources[] = { 223static struct resource yl9200_flash_resources[] = {
302{ 224 {
303 .start = YL_9200_FLASH_BASE, 225 .start = YL9200_FLASH_BASE,
304 .end = YL_9200_FLASH_BASE + YL_9200_FLASH_SIZE - 1, 226 .end = YL9200_FLASH_BASE + YL9200_FLASH_SIZE - 1,
305 .flags = IORESOURCE_MEM, 227 .flags = IORESOURCE_MEM,
306 } 228 }
307}; 229};
308 230
309static struct platform_device yl_9200_flash = { 231static struct platform_device yl9200_flash = {
310 .name = "physmap-flash", 232 .name = "physmap-flash",
311 .id = 0, 233 .id = 0,
312 .dev = { 234 .dev = {
313 .platform_data = &yl_9200_flash_data, 235 .platform_data = &yl9200_flash_data,
314 }, 236 },
315 .resource = yl_9200_flash_resources, 237 .resource = yl9200_flash_resources,
316 .num_resources = ARRAY_SIZE(yl_9200_flash_resources), 238 .num_resources = ARRAY_SIZE(yl9200_flash_resources),
317}; 239};
318 240
319 241/*
320static struct gpio_led yl_9200_leds[] = { 242 * I2C (TWI)
321/*D2 &D3 are passed directly in via at91_init_leds*/ 243 */
322 { 244static struct i2c_board_info __initdata yl9200_i2c_devices[] = {
323 .name = "led4", /*D4*/ 245 { /* EEPROM */
324 .gpio = AT91_PIN_PB15, 246 I2C_BOARD_INFO("24c128", 0x50),
325 .active_low = 1,
326 .default_trigger = "heartbeat",
327 /*.default_trigger = "timer",*/
328 },
329 {
330 .name = "led5", /*D5*/
331 .gpio = AT91_PIN_PB8,
332 .active_low = 1,
333 .default_trigger = "heartbeat",
334 }
335};
336
337//static struct gpio_sounder yl_9200_sounder[] = {*/
338/*This is a simple speaker attached to a gpo line*/
339
340// {
341// .name = "Speaker", /*LS1*/
342// .gpio = AT91_PIN_PA22,
343// .active_low = 0,
344// .default_trigger = "heartbeat",
345 /*.default_trigger = "timer",*/
346// },
347//};
348
349
350
351static struct i2c_board_info __initdata yl_9200_i2c_devices[] = {
352 {
353 /*TODO*/
354 I2C_BOARD_INFO("CS4334", 0x00),
355 } 247 }
356}; 248};
357 249
358 250/*
359 /*
360 * GPIO Buttons 251 * GPIO Buttons
361 */ 252*/
362#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) 253#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
363static struct gpio_keys_button yl_9200_buttons[] = { 254static struct gpio_keys_button yl9200_buttons[] = {
364 { 255 {
365 .gpio = AT91_PIN_PA24, 256 .gpio = AT91_PIN_PA24,
366 .code = BTN_2, 257 .code = BTN_2,
367 .desc = "SW2", 258 .desc = "SW2",
368 .active_low = 1, 259 .active_low = 1,
369 .wakeup = 1, 260 .wakeup = 1,
370 }, 261 },
371 { 262 {
372 .gpio = AT91_PIN_PB1, 263 .gpio = AT91_PIN_PB1,
373 .code = BTN_3, 264 .code = BTN_3,
374 .desc = "SW3", 265 .desc = "SW3",
375 .active_low = 1, 266 .active_low = 1,
376 .wakeup = 1, 267 .wakeup = 1,
377 }, 268 },
378 { 269 {
379 .gpio = AT91_PIN_PB2, 270 .gpio = AT91_PIN_PB2,
380 .code = BTN_4, 271 .code = BTN_4,
381 .desc = "SW4", 272 .desc = "SW4",
382 .active_low = 1, 273 .active_low = 1,
383 .wakeup = 1, 274 .wakeup = 1,
384 }, 275 },
385 { 276 {
386 .gpio = AT91_PIN_PB6, 277 .gpio = AT91_PIN_PB6,
387 .code = BTN_5, 278 .code = BTN_5,
388 .desc = "SW5", 279 .desc = "SW5",
389 .active_low = 1, 280 .active_low = 1,
390 .wakeup = 1, 281 .wakeup = 1,
391 }, 282 }
392
393}; 283};
394 284
395static struct gpio_keys_platform_data yl_9200_button_data = { 285static struct gpio_keys_platform_data yl9200_button_data = {
396 .buttons = yl_9200_buttons, 286 .buttons = yl9200_buttons,
397 .nbuttons = ARRAY_SIZE(yl_9200_buttons), 287 .nbuttons = ARRAY_SIZE(yl9200_buttons),
398}; 288};
399 289
400static struct platform_device yl_9200_button_device = { 290static struct platform_device yl9200_button_device = {
401 .name = "gpio-keys", 291 .name = "gpio-keys",
402 .id = -1, 292 .id = -1,
403 .num_resources = 0, 293 .num_resources = 0,
404 .dev = { 294 .dev = {
405 .platform_data = &yl_9200_button_data, 295 .platform_data = &yl9200_button_data,
406 } 296 }
407}; 297};
408 298
409static void __init yl_9200_add_device_buttons(void) 299static void __init yl9200_add_device_buttons(void)
410{ 300{
411 //SW2 301 at91_set_gpio_input(AT91_PIN_PA24, 1); /* SW2 */
412 at91_set_gpio_input(AT91_PIN_PA24, 0);
413 at91_set_deglitch(AT91_PIN_PA24, 1); 302 at91_set_deglitch(AT91_PIN_PA24, 1);
414 303 at91_set_gpio_input(AT91_PIN_PB1, 1); /* SW3 */
415 //SW3
416 at91_set_gpio_input(AT91_PIN_PB1, 0);
417 at91_set_deglitch(AT91_PIN_PB1, 1); 304 at91_set_deglitch(AT91_PIN_PB1, 1);
418 //SW4 305 at91_set_gpio_input(AT91_PIN_PB2, 1); /* SW4 */
419 at91_set_gpio_input(AT91_PIN_PB2, 0);
420 at91_set_deglitch(AT91_PIN_PB2, 1); 306 at91_set_deglitch(AT91_PIN_PB2, 1);
421 307 at91_set_gpio_input(AT91_PIN_PB6, 1); /* SW5 */
422 //SW5
423 at91_set_gpio_input(AT91_PIN_PB6, 0);
424 at91_set_deglitch(AT91_PIN_PB6, 1); 308 at91_set_deglitch(AT91_PIN_PB6, 1);
425 309
310 /* Enable buttons (Sheet 5) */
311 at91_set_gpio_output(AT91_PIN_PB7, 1);
312
313 platform_device_register(&yl9200_button_device);
314}
315#else
316static void __init yl9200_add_device_buttons(void) {}
317#endif
318
319/*
320 * Touchscreen
321 */
322#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
323static int ads7843_pendown_state(void)
324{
325 return !at91_get_gpio_value(AT91_PIN_PB11); /* Touchscreen PENIRQ */
326}
327
328static struct ads7846_platform_data ads_info = {
329 .model = 7843,
330 .x_min = 150,
331 .x_max = 3830,
332 .y_min = 190,
333 .y_max = 3830,
334 .vref_delay_usecs = 100,
335
336 /* For a 8" touch-screen */
337 // .x_plate_ohms = 603,
338 // .y_plate_ohms = 332,
339
340 /* For a 10.4" touch-screen */
341 // .x_plate_ohms = 611,
342 // .y_plate_ohms = 325,
343
344 .x_plate_ohms = 576,
345 .y_plate_ohms = 366,
346
347 .pressure_max = 15000, /* generally nonsense on the 7843 */
348 .debounce_max = 1,
349 .debounce_rep = 0,
350 .debounce_tol = (~0),
351 .get_pendown_state = ads7843_pendown_state,
352};
426 353
427 at91_set_gpio_output(AT91_PIN_PB7, 1); /* #TURN BUTTONS ON, SHEET 5 of schematics */ 354static void __init yl9200_add_device_ts(void)
428 platform_device_register(&yl_9200_button_device); 355{
356 at91_set_gpio_input(AT91_PIN_PB11, 1); /* Touchscreen interrupt pin */
357 at91_set_gpio_input(AT91_PIN_PB10, 1); /* Touchscreen BUSY signal - not used! */
429} 358}
430#else 359#else
431static void __init yl_9200_add_device_buttons(void) {} 360static void __init yl9200_add_device_ts(void) {}
361#endif
362
363/*
364 * SPI devices
365 */
366static struct spi_board_info yl9200_spi_devices[] = {
367#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
368 { /* Touchscreen */
369 .modalias = "ads7846",
370 .chip_select = 0,
371 .max_speed_hz = 5000 * 26,
372 .platform_data = &ads_info,
373 .irq = AT91_PIN_PB11,
374 },
432#endif 375#endif
376 { /* CAN */
377 .modalias = "mcp2510",
378 .chip_select = 1,
379 .max_speed_hz = 25000 * 26,
380 .irq = AT91_PIN_PC0,
381 }
382};
433 383
384/*
385 * LCD / VGA
386 *
387 * EPSON S1D13806 FB (discontinued chip)
388 * EPSON S1D13506 FB
389 */
434#if defined(CONFIG_FB_S1D135XX) || defined(CONFIG_FB_S1D13XXX_MODULE) 390#if defined(CONFIG_FB_S1D135XX) || defined(CONFIG_FB_S1D13XXX_MODULE)
435#include <video/s1d13xxxfb.h> 391#include <video/s1d13xxxfb.h>
436 392
437/* EPSON S1D13806 FB (discontinued chip)*/
438/* EPSON S1D13506 FB */
439
440#define AT91_FB_REG_BASE 0x80000000L 393#define AT91_FB_REG_BASE 0x80000000L
441#define AT91_FB_REG_SIZE 0x200 394#define AT91_FB_REG_SIZE 0x200
442#define AT91_FB_VMEM_BASE 0x80200000L 395#define AT91_FB_VMEM_BASE 0x80200000L
443#define AT91_FB_VMEM_SIZE 0x200000L 396#define AT91_FB_VMEM_SIZE 0x200000L
444 397
445/*#define S1D_DISPLAY_WIDTH 640*/ 398static void __init yl9200_init_video(void)
446/*#define S1D_DISPLAY_HEIGHT 480*/
447
448
449static void __init yl_9200_init_video(void)
450{ 399{
451 at91_sys_write(AT91_PIOC + PIO_ASR,AT91_PIN_PC6); 400 /* NWAIT Signal */
452 at91_sys_write(AT91_PIOC + PIO_BSR,0); 401 at91_set_A_periph(AT91_PIN_PC6, 0);
453 at91_sys_write(AT91_PIOC + PIO_ASR,AT91_PIN_PC6);
454
455 at91_sys_write( AT91_SMC_CSR(2),
456 AT91_SMC_NWS_(0x4) |
457 AT91_SMC_WSEN |
458 AT91_SMC_TDF_(0x100) |
459 AT91_SMC_DBW
460 );
461
462
463 402
403 /* Initialization of the Static Memory Controller for Chip Select 2 */
404 at91_sys_write(AT91_SMC_CSR(2), AT91_SMC_DBW_16 /* 16 bit */
405 | AT91_SMC_WSEN | AT91_SMC_NWS_(0x4) /* wait states */
406 | AT91_SMC_TDF_(0x100) /* float time */
407 );
464} 408}
465 409
466 410static struct s1d13xxxfb_regval yl9200_s1dfb_initregs[] =
467static struct s1d13xxxfb_regval yl_9200_s1dfb_initregs[] =
468{ 411{
469 {S1DREG_MISC, 0x00}, /* Miscellaneous Register*/ 412 {S1DREG_MISC, 0x00}, /* Miscellaneous Register*/
470 {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/ 413 {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/
471 {S1DREG_GPIO_CNF0, 0x00}, /* General IO Pins Configuration Register*/ 414 {S1DREG_GPIO_CNF0, 0x00}, /* General IO Pins Configuration Register*/
472 {S1DREG_GPIO_CTL0, 0x00}, /* General IO Pins Control Register*/ 415 {S1DREG_GPIO_CTL0, 0x00}, /* General IO Pins Control Register*/
473 {S1DREG_CLK_CNF, 0x11}, /* Memory Clock Configuration Register*/ 416 {S1DREG_CLK_CNF, 0x11}, /* Memory Clock Configuration Register*/
474 {S1DREG_LCD_CLK_CNF, 0x10}, /* LCD Pixel Clock Configuration Register*/ 417 {S1DREG_LCD_CLK_CNF, 0x10}, /* LCD Pixel Clock Configuration Register*/
475 {S1DREG_CRT_CLK_CNF, 0x12}, /* CRT/TV Pixel Clock Configuration Register*/ 418 {S1DREG_CRT_CLK_CNF, 0x12}, /* CRT/TV Pixel Clock Configuration Register*/
476 {S1DREG_MPLUG_CLK_CNF, 0x01}, /* MediaPlug Clock Configuration Register*/ 419 {S1DREG_MPLUG_CLK_CNF, 0x01}, /* MediaPlug Clock Configuration Register*/
477 {S1DREG_CPU2MEM_WST_SEL, 0x02}, /* CPU To Memory Wait State Select Register*/ 420 {S1DREG_CPU2MEM_WST_SEL, 0x02}, /* CPU To Memory Wait State Select Register*/
478 {S1DREG_MEM_CNF, 0x00}, /* Memory Configuration Register*/ 421 {S1DREG_MEM_CNF, 0x00}, /* Memory Configuration Register*/
479 {S1DREG_SDRAM_REF_RATE, 0x04}, /* DRAM Refresh Rate Register, MCLK source*/ 422 {S1DREG_SDRAM_REF_RATE, 0x04}, /* DRAM Refresh Rate Register, MCLK source*/
480 {S1DREG_SDRAM_TC0, 0x12}, /* DRAM Timings Control Register 0*/ 423 {S1DREG_SDRAM_TC0, 0x12}, /* DRAM Timings Control Register 0*/
481 {S1DREG_SDRAM_TC1, 0x02}, /* DRAM Timings Control Register 1*/ 424 {S1DREG_SDRAM_TC1, 0x02}, /* DRAM Timings Control Register 1*/
482 {S1DREG_PANEL_TYPE, 0x25}, /* Panel Type Register*/ 425 {S1DREG_PANEL_TYPE, 0x25}, /* Panel Type Register*/
483 {S1DREG_MOD_RATE, 0x00}, /* MOD Rate Register*/ 426 {S1DREG_MOD_RATE, 0x00}, /* MOD Rate Register*/
484 {S1DREG_LCD_DISP_HWIDTH, 0x4F}, /* LCD Horizontal Display Width Register*/ 427 {S1DREG_LCD_DISP_HWIDTH, 0x4F}, /* LCD Horizontal Display Width Register*/
485 {S1DREG_LCD_NDISP_HPER, 0x13}, /* LCD Horizontal Non-Display Period Register*/ 428 {S1DREG_LCD_NDISP_HPER, 0x13}, /* LCD Horizontal Non-Display Period Register*/
486 {S1DREG_TFT_FPLINE_START, 0x01}, /* TFT FPLINE Start Position Register*/ 429 {S1DREG_TFT_FPLINE_START, 0x01}, /* TFT FPLINE Start Position Register*/
487 {S1DREG_TFT_FPLINE_PWIDTH, 0x0c}, /* TFT FPLINE Pulse Width Register*/ 430 {S1DREG_TFT_FPLINE_PWIDTH, 0x0c}, /* TFT FPLINE Pulse Width Register*/
488 {S1DREG_LCD_DISP_VHEIGHT0, 0xDF}, /* LCD Vertical Display Height Register 0*/ 431 {S1DREG_LCD_DISP_VHEIGHT0, 0xDF}, /* LCD Vertical Display Height Register 0*/
489 {S1DREG_LCD_DISP_VHEIGHT1, 0x01}, /* LCD Vertical Display Height Register 1*/ 432 {S1DREG_LCD_DISP_VHEIGHT1, 0x01}, /* LCD Vertical Display Height Register 1*/
490 {S1DREG_LCD_NDISP_VPER, 0x2c}, /* LCD Vertical Non-Display Period Register*/ 433 {S1DREG_LCD_NDISP_VPER, 0x2c}, /* LCD Vertical Non-Display Period Register*/
491 {S1DREG_TFT_FPFRAME_START, 0x0a}, /* TFT FPFRAME Start Position Register*/ 434 {S1DREG_TFT_FPFRAME_START, 0x0a}, /* TFT FPFRAME Start Position Register*/
492 {S1DREG_TFT_FPFRAME_PWIDTH, 0x02}, /* TFT FPFRAME Pulse Width Register*/ 435 {S1DREG_TFT_FPFRAME_PWIDTH, 0x02}, /* TFT FPFRAME Pulse Width Register*/
493 {S1DREG_LCD_DISP_MODE, 0x05}, /* LCD Display Mode Register*/ 436 {S1DREG_LCD_DISP_MODE, 0x05}, /* LCD Display Mode Register*/
494 {S1DREG_LCD_MISC, 0x01}, /* LCD Miscellaneous Register*/ 437 {S1DREG_LCD_MISC, 0x01}, /* LCD Miscellaneous Register*/
495 {S1DREG_LCD_DISP_START0, 0x00}, /* LCD Display Start Address Register 0*/ 438 {S1DREG_LCD_DISP_START0, 0x00}, /* LCD Display Start Address Register 0*/
496 {S1DREG_LCD_DISP_START1, 0x00}, /* LCD Display Start Address Register 1*/ 439 {S1DREG_LCD_DISP_START1, 0x00}, /* LCD Display Start Address Register 1*/
497 {S1DREG_LCD_DISP_START2, 0x00}, /* LCD Display Start Address Register 2*/ 440 {S1DREG_LCD_DISP_START2, 0x00}, /* LCD Display Start Address Register 2*/
498 {S1DREG_LCD_MEM_OFF0, 0x80}, /* LCD Memory Address Offset Register 0*/ 441 {S1DREG_LCD_MEM_OFF0, 0x80}, /* LCD Memory Address Offset Register 0*/
499 {S1DREG_LCD_MEM_OFF1, 0x02}, /* LCD Memory Address Offset Register 1*/ 442 {S1DREG_LCD_MEM_OFF1, 0x02}, /* LCD Memory Address Offset Register 1*/
500 {S1DREG_LCD_PIX_PAN, 0x03}, /* LCD Pixel Panning Register*/ 443 {S1DREG_LCD_PIX_PAN, 0x03}, /* LCD Pixel Panning Register*/
501 {S1DREG_LCD_DISP_FIFO_HTC, 0x00}, /* LCD Display FIFO High Threshold Control Register*/ 444 {S1DREG_LCD_DISP_FIFO_HTC, 0x00}, /* LCD Display FIFO High Threshold Control Register*/
502 {S1DREG_LCD_DISP_FIFO_LTC, 0x00}, /* LCD Display FIFO Low Threshold Control Register*/ 445 {S1DREG_LCD_DISP_FIFO_LTC, 0x00}, /* LCD Display FIFO Low Threshold Control Register*/
503 {S1DREG_CRT_DISP_HWIDTH, 0x4F}, /* CRT/TV Horizontal Display Width Register*/ 446 {S1DREG_CRT_DISP_HWIDTH, 0x4F}, /* CRT/TV Horizontal Display Width Register*/
504 {S1DREG_CRT_NDISP_HPER, 0x13}, /* CRT/TV Horizontal Non-Display Period Register*/ 447 {S1DREG_CRT_NDISP_HPER, 0x13}, /* CRT/TV Horizontal Non-Display Period Register*/
505 {S1DREG_CRT_HRTC_START, 0x01}, /* CRT/TV HRTC Start Position Register*/ 448 {S1DREG_CRT_HRTC_START, 0x01}, /* CRT/TV HRTC Start Position Register*/
506 {S1DREG_CRT_HRTC_PWIDTH, 0x0B}, /* CRT/TV HRTC Pulse Width Register*/ 449 {S1DREG_CRT_HRTC_PWIDTH, 0x0B}, /* CRT/TV HRTC Pulse Width Register*/
507 {S1DREG_CRT_DISP_VHEIGHT0, 0xDF}, /* CRT/TV Vertical Display Height Register 0*/ 450 {S1DREG_CRT_DISP_VHEIGHT0, 0xDF}, /* CRT/TV Vertical Display Height Register 0*/
508 {S1DREG_CRT_DISP_VHEIGHT1, 0x01}, /* CRT/TV Vertical Display Height Register 1*/ 451 {S1DREG_CRT_DISP_VHEIGHT1, 0x01}, /* CRT/TV Vertical Display Height Register 1*/
509 {S1DREG_CRT_NDISP_VPER, 0x2B}, /* CRT/TV Vertical Non-Display Period Register*/ 452 {S1DREG_CRT_NDISP_VPER, 0x2B}, /* CRT/TV Vertical Non-Display Period Register*/
510 {S1DREG_CRT_VRTC_START, 0x09}, /* CRT/TV VRTC Start Position Register*/ 453 {S1DREG_CRT_VRTC_START, 0x09}, /* CRT/TV VRTC Start Position Register*/
511 {S1DREG_CRT_VRTC_PWIDTH, 0x01}, /* CRT/TV VRTC Pulse Width Register*/ 454 {S1DREG_CRT_VRTC_PWIDTH, 0x01}, /* CRT/TV VRTC Pulse Width Register*/
512 {S1DREG_TV_OUT_CTL, 0x18}, /* TV Output Control Register */ 455 {S1DREG_TV_OUT_CTL, 0x18}, /* TV Output Control Register */
513 {S1DREG_CRT_DISP_MODE, 0x05}, /* CRT/TV Display Mode Register, 16BPP*/ 456 {S1DREG_CRT_DISP_MODE, 0x05}, /* CRT/TV Display Mode Register, 16BPP*/
514 {S1DREG_CRT_DISP_START0, 0x00}, /* CRT/TV Display Start Address Register 0*/ 457 {S1DREG_CRT_DISP_START0, 0x00}, /* CRT/TV Display Start Address Register 0*/
515 {S1DREG_CRT_DISP_START1, 0x00}, /* CRT/TV Display Start Address Register 1*/ 458 {S1DREG_CRT_DISP_START1, 0x00}, /* CRT/TV Display Start Address Register 1*/
516 {S1DREG_CRT_DISP_START2, 0x00}, /* CRT/TV Display Start Address Register 2*/ 459 {S1DREG_CRT_DISP_START2, 0x00}, /* CRT/TV Display Start Address Register 2*/
517 {S1DREG_CRT_MEM_OFF0, 0x80}, /* CRT/TV Memory Address Offset Register 0*/ 460 {S1DREG_CRT_MEM_OFF0, 0x80}, /* CRT/TV Memory Address Offset Register 0*/
518 {S1DREG_CRT_MEM_OFF1, 0x02}, /* CRT/TV Memory Address Offset Register 1*/ 461 {S1DREG_CRT_MEM_OFF1, 0x02}, /* CRT/TV Memory Address Offset Register 1*/
519 {S1DREG_CRT_PIX_PAN, 0x00}, /* CRT/TV Pixel Panning Register*/ 462 {S1DREG_CRT_PIX_PAN, 0x00}, /* CRT/TV Pixel Panning Register*/
520 {S1DREG_CRT_DISP_FIFO_HTC, 0x00}, /* CRT/TV Display FIFO High Threshold Control Register*/ 463 {S1DREG_CRT_DISP_FIFO_HTC, 0x00}, /* CRT/TV Display FIFO High Threshold Control Register*/
521 {S1DREG_CRT_DISP_FIFO_LTC, 0x00}, /* CRT/TV Display FIFO Low Threshold Control Register*/ 464 {S1DREG_CRT_DISP_FIFO_LTC, 0x00}, /* CRT/TV Display FIFO Low Threshold Control Register*/
522 {S1DREG_LCD_CUR_CTL, 0x00}, /* LCD Ink/Cursor Control Register*/ 465 {S1DREG_LCD_CUR_CTL, 0x00}, /* LCD Ink/Cursor Control Register*/
523 {S1DREG_LCD_CUR_START, 0x01}, /* LCD Ink/Cursor Start Address Register*/ 466 {S1DREG_LCD_CUR_START, 0x01}, /* LCD Ink/Cursor Start Address Register*/
524 {S1DREG_LCD_CUR_XPOS0, 0x00}, /* LCD Cursor X Position Register 0*/ 467 {S1DREG_LCD_CUR_XPOS0, 0x00}, /* LCD Cursor X Position Register 0*/
525 {S1DREG_LCD_CUR_XPOS1, 0x00}, /* LCD Cursor X Position Register 1*/ 468 {S1DREG_LCD_CUR_XPOS1, 0x00}, /* LCD Cursor X Position Register 1*/
526 {S1DREG_LCD_CUR_YPOS0, 0x00}, /* LCD Cursor Y Position Register 0*/ 469 {S1DREG_LCD_CUR_YPOS0, 0x00}, /* LCD Cursor Y Position Register 0*/
527 {S1DREG_LCD_CUR_YPOS1, 0x00}, /* LCD Cursor Y Position Register 1*/ 470 {S1DREG_LCD_CUR_YPOS1, 0x00}, /* LCD Cursor Y Position Register 1*/
528 {S1DREG_LCD_CUR_BCTL0, 0x00}, /* LCD Ink/Cursor Blue Color 0 Register*/ 471 {S1DREG_LCD_CUR_BCTL0, 0x00}, /* LCD Ink/Cursor Blue Color 0 Register*/
529 {S1DREG_LCD_CUR_GCTL0, 0x00}, /* LCD Ink/Cursor Green Color 0 Register*/ 472 {S1DREG_LCD_CUR_GCTL0, 0x00}, /* LCD Ink/Cursor Green Color 0 Register*/
530 {S1DREG_LCD_CUR_RCTL0, 0x00}, /* LCD Ink/Cursor Red Color 0 Register*/ 473 {S1DREG_LCD_CUR_RCTL0, 0x00}, /* LCD Ink/Cursor Red Color 0 Register*/
531 {S1DREG_LCD_CUR_BCTL1, 0x1F}, /* LCD Ink/Cursor Blue Color 1 Register*/ 474 {S1DREG_LCD_CUR_BCTL1, 0x1F}, /* LCD Ink/Cursor Blue Color 1 Register*/
532 {S1DREG_LCD_CUR_GCTL1, 0x3F}, /* LCD Ink/Cursor Green Color 1 Register*/ 475 {S1DREG_LCD_CUR_GCTL1, 0x3F}, /* LCD Ink/Cursor Green Color 1 Register*/
533 {S1DREG_LCD_CUR_RCTL1, 0x1F}, /* LCD Ink/Cursor Red Color 1 Register*/ 476 {S1DREG_LCD_CUR_RCTL1, 0x1F}, /* LCD Ink/Cursor Red Color 1 Register*/
534 {S1DREG_LCD_CUR_FIFO_HTC, 0x00}, /* LCD Ink/Cursor FIFO Threshold Register*/ 477 {S1DREG_LCD_CUR_FIFO_HTC, 0x00}, /* LCD Ink/Cursor FIFO Threshold Register*/
535 {S1DREG_CRT_CUR_CTL, 0x00}, /* CRT/TV Ink/Cursor Control Register*/ 478 {S1DREG_CRT_CUR_CTL, 0x00}, /* CRT/TV Ink/Cursor Control Register*/
536 {S1DREG_CRT_CUR_START, 0x01}, /* CRT/TV Ink/Cursor Start Address Register*/ 479 {S1DREG_CRT_CUR_START, 0x01}, /* CRT/TV Ink/Cursor Start Address Register*/
537 {S1DREG_CRT_CUR_XPOS0, 0x00}, /* CRT/TV Cursor X Position Register 0*/ 480 {S1DREG_CRT_CUR_XPOS0, 0x00}, /* CRT/TV Cursor X Position Register 0*/
538 {S1DREG_CRT_CUR_XPOS1, 0x00}, /* CRT/TV Cursor X Position Register 1*/ 481 {S1DREG_CRT_CUR_XPOS1, 0x00}, /* CRT/TV Cursor X Position Register 1*/
539 {S1DREG_CRT_CUR_YPOS0, 0x00}, /* CRT/TV Cursor Y Position Register 0*/ 482 {S1DREG_CRT_CUR_YPOS0, 0x00}, /* CRT/TV Cursor Y Position Register 0*/
540 {S1DREG_CRT_CUR_YPOS1, 0x00}, /* CRT/TV Cursor Y Position Register 1*/ 483 {S1DREG_CRT_CUR_YPOS1, 0x00}, /* CRT/TV Cursor Y Position Register 1*/
541 {S1DREG_CRT_CUR_BCTL0, 0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register*/ 484 {S1DREG_CRT_CUR_BCTL0, 0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register*/
542 {S1DREG_CRT_CUR_GCTL0, 0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register*/ 485 {S1DREG_CRT_CUR_GCTL0, 0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register*/
543 {S1DREG_CRT_CUR_RCTL0, 0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register*/ 486 {S1DREG_CRT_CUR_RCTL0, 0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register*/
544 {S1DREG_CRT_CUR_BCTL1, 0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register*/ 487 {S1DREG_CRT_CUR_BCTL1, 0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register*/
545 {S1DREG_CRT_CUR_GCTL1, 0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register*/ 488 {S1DREG_CRT_CUR_GCTL1, 0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register*/
546 {S1DREG_CRT_CUR_RCTL1, 0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register*/ 489 {S1DREG_CRT_CUR_RCTL1, 0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register*/
547 {S1DREG_CRT_CUR_FIFO_HTC, 0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register*/ 490 {S1DREG_CRT_CUR_FIFO_HTC, 0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register*/
548 {S1DREG_BBLT_CTL0, 0x00}, /* BitBlt Control Register 0*/ 491 {S1DREG_BBLT_CTL0, 0x00}, /* BitBlt Control Register 0*/
549 {S1DREG_BBLT_CTL1, 0x01}, /* BitBlt Control Register 1*/ 492 {S1DREG_BBLT_CTL1, 0x01}, /* BitBlt Control Register 1*/
550 {S1DREG_BBLT_CC_EXP, 0x00}, /* BitBlt ROP Code/Color Expansion Register*/ 493 {S1DREG_BBLT_CC_EXP, 0x00}, /* BitBlt ROP Code/Color Expansion Register*/
551 {S1DREG_BBLT_OP, 0x00}, /* BitBlt Operation Register*/ 494 {S1DREG_BBLT_OP, 0x00}, /* BitBlt Operation Register*/
552 {S1DREG_BBLT_SRC_START0, 0x00}, /* BitBlt Source Start Address Register 0*/ 495 {S1DREG_BBLT_SRC_START0, 0x00}, /* BitBlt Source Start Address Register 0*/
553 {S1DREG_BBLT_SRC_START1, 0x00}, /* BitBlt Source Start Address Register 1*/ 496 {S1DREG_BBLT_SRC_START1, 0x00}, /* BitBlt Source Start Address Register 1*/
554 {S1DREG_BBLT_SRC_START2, 0x00}, /* BitBlt Source Start Address Register 2*/ 497 {S1DREG_BBLT_SRC_START2, 0x00}, /* BitBlt Source Start Address Register 2*/
555 {S1DREG_BBLT_DST_START0, 0x00}, /* BitBlt Destination Start Address Register 0*/ 498 {S1DREG_BBLT_DST_START0, 0x00}, /* BitBlt Destination Start Address Register 0*/
556 {S1DREG_BBLT_DST_START1, 0x00}, /* BitBlt Destination Start Address Register 1*/ 499 {S1DREG_BBLT_DST_START1, 0x00}, /* BitBlt Destination Start Address Register 1*/
557 {S1DREG_BBLT_DST_START2, 0x00}, /* BitBlt Destination Start Address Register 2*/ 500 {S1DREG_BBLT_DST_START2, 0x00}, /* BitBlt Destination Start Address Register 2*/
558 {S1DREG_BBLT_MEM_OFF0, 0x00}, /* BitBlt Memory Address Offset Register 0*/ 501 {S1DREG_BBLT_MEM_OFF0, 0x00}, /* BitBlt Memory Address Offset Register 0*/
559 {S1DREG_BBLT_MEM_OFF1, 0x00}, /* BitBlt Memory Address Offset Register 1*/ 502 {S1DREG_BBLT_MEM_OFF1, 0x00}, /* BitBlt Memory Address Offset Register 1*/
560 {S1DREG_BBLT_WIDTH0, 0x00}, /* BitBlt Width Register 0*/ 503 {S1DREG_BBLT_WIDTH0, 0x00}, /* BitBlt Width Register 0*/
561 {S1DREG_BBLT_WIDTH1, 0x00}, /* BitBlt Width Register 1*/ 504 {S1DREG_BBLT_WIDTH1, 0x00}, /* BitBlt Width Register 1*/
562 {S1DREG_BBLT_HEIGHT0, 0x00}, /* BitBlt Height Register 0*/ 505 {S1DREG_BBLT_HEIGHT0, 0x00}, /* BitBlt Height Register 0*/
563 {S1DREG_BBLT_HEIGHT1, 0x00}, /* BitBlt Height Register 1*/ 506 {S1DREG_BBLT_HEIGHT1, 0x00}, /* BitBlt Height Register 1*/
564 {S1DREG_BBLT_BGC0, 0x00}, /* BitBlt Background Color Register 0*/ 507 {S1DREG_BBLT_BGC0, 0x00}, /* BitBlt Background Color Register 0*/
565 {S1DREG_BBLT_BGC1, 0x00}, /* BitBlt Background Color Register 1*/ 508 {S1DREG_BBLT_BGC1, 0x00}, /* BitBlt Background Color Register 1*/
566 {S1DREG_BBLT_FGC0, 0x00}, /* BitBlt Foreground Color Register 0*/ 509 {S1DREG_BBLT_FGC0, 0x00}, /* BitBlt Foreground Color Register 0*/
567 {S1DREG_BBLT_FGC1, 0x00}, /* BitBlt Foreground Color Register 1*/ 510 {S1DREG_BBLT_FGC1, 0x00}, /* BitBlt Foreground Color Register 1*/
568 {S1DREG_LKUP_MODE, 0x00}, /* Look-Up Table Mode Register*/ 511 {S1DREG_LKUP_MODE, 0x00}, /* Look-Up Table Mode Register*/
569 {S1DREG_LKUP_ADDR, 0x00}, /* Look-Up Table Address Register*/ 512 {S1DREG_LKUP_ADDR, 0x00}, /* Look-Up Table Address Register*/
570 {S1DREG_PS_CNF, 0x00}, /* Power Save Configuration Register*/ 513 {S1DREG_PS_CNF, 0x00}, /* Power Save Configuration Register*/
571 {S1DREG_PS_STATUS, 0x00}, /* Power Save Status Register*/ 514 {S1DREG_PS_STATUS, 0x00}, /* Power Save Status Register*/
572 {S1DREG_CPU2MEM_WDOGT, 0x00}, /* CPU-to-Memory Access Watchdog Timer Register*/ 515 {S1DREG_CPU2MEM_WDOGT, 0x00}, /* CPU-to-Memory Access Watchdog Timer Register*/
573 {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/ 516 {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/
574}; 517};
575 518
576static u64 s1dfb_dmamask = 0xffffffffUL; 519static u64 s1dfb_dmamask = DMA_BIT_MASK(32);
577 520
578static struct s1d13xxxfb_pdata yl_9200_s1dfb_pdata = { 521static struct s1d13xxxfb_pdata yl9200_s1dfb_pdata = {
579 .initregs = yl_9200_s1dfb_initregs, 522 .initregs = yl9200_s1dfb_initregs,
580 .initregssize = ARRAY_SIZE(yl_9200_s1dfb_initregs), 523 .initregssize = ARRAY_SIZE(yl9200_s1dfb_initregs),
581 .platform_init_video = yl_9200_init_video, 524 .platform_init_video = yl9200_init_video,
582}; 525};
583 526
584static struct resource yl_9200_s1dfb_resource[] = { 527static struct resource yl9200_s1dfb_resource[] = {
585 [0] = { /* video mem */ 528 [0] = { /* video mem */
586 .name = "s1d13xxxfb memory", 529 .name = "s1d13xxxfb memory",
587 /* .name = "s1d13806 memory",*/ 530 .start = AT91_FB_VMEM_BASE,
588 .start = AT91_FB_VMEM_BASE, 531 .end = AT91_FB_VMEM_BASE + AT91_FB_VMEM_SIZE -1,
589 .end = AT91_FB_VMEM_BASE + AT91_FB_VMEM_SIZE -1, 532 .flags = IORESOURCE_MEM,
590 .flags = IORESOURCE_MEM,
591 }, 533 },
592 [1] = { /* video registers */ 534 [1] = { /* video registers */
593 .name = "s1d13xxxfb registers", 535 .name = "s1d13xxxfb registers",
594 /* .name = "s1d13806 registers",*/ 536 .start = AT91_FB_REG_BASE,
595 .start = AT91_FB_REG_BASE, 537 .end = AT91_FB_REG_BASE + AT91_FB_REG_SIZE -1,
596 .end = AT91_FB_REG_BASE + AT91_FB_REG_SIZE -1, 538 .flags = IORESOURCE_MEM,
597 .flags = IORESOURCE_MEM,
598 }, 539 },
599}; 540};
600 541
601static struct platform_device yl_9200_s1dfb_device = { 542static struct platform_device yl9200_s1dfb_device = {
602 /*TODO S.Birtles , really we need the chip revision in here as well*/ 543 .name = "s1d13806fb",
603 .name = "s1d13806fb", 544 .id = -1,
604 /* .name = "s1d13506fb",*/ 545 .dev = {
605 .id = -1,
606 .dev = {
607 /*TODO theres a waring here!!*/
608 /*WARNING: vmlinux.o(.data+0x2dbc): Section mismatch: reference to .init.text: (between 'yl_9200_s1dfb_pdata' and 's1dfb_dmamask')*/
609 .dma_mask = &s1dfb_dmamask, 546 .dma_mask = &s1dfb_dmamask,
610 .coherent_dma_mask = 0xffffffff, 547 .coherent_dma_mask = DMA_BIT_MASK(32),
611 .platform_data = &yl_9200_s1dfb_pdata, 548 .platform_data = &yl9200_s1dfb_pdata,
612 }, 549 },
613 .resource = yl_9200_s1dfb_resource, 550 .resource = yl9200_s1dfb_resource,
614 .num_resources = ARRAY_SIZE(yl_9200_s1dfb_resource), 551 .num_resources = ARRAY_SIZE(yl9200_s1dfb_resource),
615}; 552};
616 553
617void __init yl_9200_add_device_video(void) 554void __init yl9200_add_device_video(void)
618{ 555{
619 platform_device_register(&yl_9200_s1dfb_device); 556 platform_device_register(&yl9200_s1dfb_device);
620} 557}
621#else 558#else
622 void __init yl_9200_add_device_video(void) {} 559void __init yl9200_add_device_video(void) {}
623#endif 560#endif
624 561
625/*this is not called first , yl_9200_map_io is called first*/ 562
626static void __init yl_9200_board_init(void) 563static void __init yl9200_board_init(void)
627{ 564{
628 /* Serial */ 565 /* Serial */
629 at91_add_device_serial(); 566 at91_add_device_serial();
630 /* Ethernet */ 567 /* Ethernet */
631 at91_add_device_eth(&yl_9200_eth_data); 568 at91_add_device_eth(&yl9200_eth_data);
632 /* USB Host */ 569 /* USB Host */
633 at91_add_device_usbh(&yl_9200_usbh_data); 570 at91_add_device_usbh(&yl9200_usbh_data);
634 /* USB Device */ 571 /* USB Device */
635 at91_add_device_udc(&yl_9200_udc_data); 572 at91_add_device_udc(&yl9200_udc_data);
636 /* pullup_pin it is actually active low, but this is not needed, driver sets it up */
637 /*at91_set_multi_drive(yl_9200_udc_data.pullup_pin, 0);*/
638
639 /* Compact Flash */
640 /*at91_add_device_cf(&yl_9200_cf_data);*/
641
642 /* I2C */ 573 /* I2C */
643 at91_add_device_i2c(yl_9200_i2c_devices, ARRAY_SIZE(yl_9200_i2c_devices)); 574 at91_add_device_i2c(yl9200_i2c_devices, ARRAY_SIZE(yl9200_i2c_devices));
644 /* SPI */ 575 /* MMC */
645 /*TODO YL9200 we have 2 spi interfaces touch screen & CAN*/ 576 at91_add_device_mmc(0, &yl9200_mmc_data);
646 /* AT91_PIN_PA5, AT91_PIN_PA6 , are used on the max 485 NOT SPI*/
647
648 /*touch screen and CAN*/
649 at91_add_device_spi(yl_9200_spi_devices, ARRAY_SIZE(yl_9200_spi_devices));
650
651 /*Basically the TS uses PB11 & PB10 , PB11 is configured by the SPI system BP10 IS NOT USED!!*/
652 /* we need this incase the board is running without a touch screen*/
653 #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
654 at91_init_device_ts(); /*init the touch screen device*/
655 #endif
656 /* DataFlash card */
657 at91_add_device_mmc(0, &yl_9200_mmc_data);
658 /* NAND */ 577 /* NAND */
659 at91_add_device_nand(&yl_9200_nand_data); 578 at91_add_device_nand(&yl9200_nand_data);
660 /* NOR Flash */ 579 /* NOR Flash */
661 platform_device_register(&yl_9200_flash); 580 platform_device_register(&yl9200_flash);
662 /* LEDs. Note!! this does not include the led's we passed for the processor status */ 581#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
663 at91_gpio_leds(yl_9200_leds, ARRAY_SIZE(yl_9200_leds)); 582 /* SPI */
664 /* VGA */ 583 at91_add_device_spi(yl9200_spi_devices, ARRAY_SIZE(yl9200_spi_devices));
665 /*this is self registered by including the s1d13xxx chip in the kernel build*/ 584 /* Touchscreen */
666 yl_9200_add_device_video(); 585 yl9200_add_device_ts();
586#endif
587 /* LEDs. */
588 at91_gpio_leds(yl9200_leds, ARRAY_SIZE(yl9200_leds));
667 /* Push Buttons */ 589 /* Push Buttons */
668 yl_9200_add_device_buttons(); 590 yl9200_add_device_buttons();
669 /*TODO fixup the Sounder */ 591 /* VGA */
670// yl_9200_add_device_sounder(yl_9200_sounder,ARRAY_SIZE(yl_9200_sounder)); 592 yl9200_add_device_video();
671
672} 593}
673 594
674MACHINE_START(YL9200, "uCdragon YL-9200") 595MACHINE_START(YL9200, "uCdragon YL-9200")
675 /* Maintainer: S.Birtles*/ 596 /* Maintainer: S.Birtles */
676 .phys_io = AT91_BASE_SYS, 597 .phys_io = AT91_BASE_SYS,
677 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, 598 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
678 .boot_params = AT91_SDRAM_BASE + 0x100, 599 .boot_params = AT91_SDRAM_BASE + 0x100,
679 .timer = &at91rm9200_timer, 600 .timer = &at91rm9200_timer,
680 .map_io = yl_9200_map_io, 601 .map_io = yl9200_map_io,
681 .init_irq = yl_9200_init_irq, 602 .init_irq = yl9200_init_irq,
682 .init_machine = yl_9200_board_init, 603 .init_machine = yl9200_board_init,
683MACHINE_END 604MACHINE_END
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-22 23:13:14 -0400