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authorAndrew Victor <andrew@sanpeople.com>2007-02-08 04:25:38 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-02-08 09:55:27 -0500
commitc177a1e75a07237efe1f68fbf430892fdf2bb868 (patch)
tree4ee68b4037cbe5c64c4385bb1d903270703db90c /arch/arm/mach-at91/at91sam9260.c
parente6d92e6397634ac7d2e80b16c52f0dfab9b673b4 (diff)
[ARM] 4147/1: AT91: Define Timer/Counter clocks.
Define the Timer/Counter Unit clocks on the AT91RM9200, AT91SAM9260 and AT91SAM9261 processors. Original patch from David Brownell. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-at91/at91sam9260.c')
-rw-r--r--arch/arm/mach-at91/at91sam9260.c38
1 files changed, 36 insertions, 2 deletions
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index ffc4c0944740..e03ee625f40c 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -107,6 +107,21 @@ static struct clk spi1_clk = {
107 .pmc_mask = 1 << AT91SAM9260_ID_SPI1, 107 .pmc_mask = 1 << AT91SAM9260_ID_SPI1,
108 .type = CLK_TYPE_PERIPHERAL, 108 .type = CLK_TYPE_PERIPHERAL,
109}; 109};
110static struct clk tc0_clk = {
111 .name = "tc0_clk",
112 .pmc_mask = 1 << AT91SAM9260_ID_TC0,
113 .type = CLK_TYPE_PERIPHERAL,
114};
115static struct clk tc1_clk = {
116 .name = "tc1_clk",
117 .pmc_mask = 1 << AT91SAM9260_ID_TC1,
118 .type = CLK_TYPE_PERIPHERAL,
119};
120static struct clk tc2_clk = {
121 .name = "tc2_clk",
122 .pmc_mask = 1 << AT91SAM9260_ID_TC2,
123 .type = CLK_TYPE_PERIPHERAL,
124};
110static struct clk ohci_clk = { 125static struct clk ohci_clk = {
111 .name = "ohci_clk", 126 .name = "ohci_clk",
112 .pmc_mask = 1 << AT91SAM9260_ID_UHP, 127 .pmc_mask = 1 << AT91SAM9260_ID_UHP,
@@ -137,6 +152,21 @@ static struct clk usart5_clk = {
137 .pmc_mask = 1 << AT91SAM9260_ID_US5, 152 .pmc_mask = 1 << AT91SAM9260_ID_US5,
138 .type = CLK_TYPE_PERIPHERAL, 153 .type = CLK_TYPE_PERIPHERAL,
139}; 154};
155static struct clk tc3_clk = {
156 .name = "tc3_clk",
157 .pmc_mask = 1 << AT91SAM9260_ID_TC3,
158 .type = CLK_TYPE_PERIPHERAL,
159};
160static struct clk tc4_clk = {
161 .name = "tc4_clk",
162 .pmc_mask = 1 << AT91SAM9260_ID_TC4,
163 .type = CLK_TYPE_PERIPHERAL,
164};
165static struct clk tc5_clk = {
166 .name = "tc5_clk",
167 .pmc_mask = 1 << AT91SAM9260_ID_TC5,
168 .type = CLK_TYPE_PERIPHERAL,
169};
140 170
141static struct clk *periph_clocks[] __initdata = { 171static struct clk *periph_clocks[] __initdata = {
142 &pioA_clk, 172 &pioA_clk,
@@ -152,14 +182,18 @@ static struct clk *periph_clocks[] __initdata = {
152 &spi0_clk, 182 &spi0_clk,
153 &spi1_clk, 183 &spi1_clk,
154 // ssc 184 // ssc
155 // tc0 .. tc2 185 &tc0_clk,
186 &tc1_clk,
187 &tc2_clk,
156 &ohci_clk, 188 &ohci_clk,
157 &ether_clk, 189 &ether_clk,
158 &isi_clk, 190 &isi_clk,
159 &usart3_clk, 191 &usart3_clk,
160 &usart4_clk, 192 &usart4_clk,
161 &usart5_clk, 193 &usart5_clk,
162 // tc3 .. tc5 194 &tc3_clk,
195 &tc4_clk,
196 &tc5_clk,
163 // irq0 .. irq2 197 // irq0 .. irq2
164}; 198};
165 199