diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2008-08-05 11:14:15 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-08-07 04:55:48 -0400 |
commit | a09e64fbc0094e3073dbb09c3b4bfe4ab669244b (patch) | |
tree | 69689f467179891b498bd7423fcf61925173db31 /arch/arm/mach-aaec2000 | |
parent | a1b81a84fff05dbfef45b7012c26e1fee9973e5d (diff) |
[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach
This just leaves include/asm-arm/plat-* to deal with.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-aaec2000')
-rw-r--r-- | arch/arm/mach-aaec2000/aaed2000.c | 4 | ||||
-rw-r--r-- | arch/arm/mach-aaec2000/core.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-aaec2000/include/mach/aaec2000.h | 207 | ||||
-rw-r--r-- | arch/arm/mach-aaec2000/include/mach/aaed2000.h | 40 | ||||
-rw-r--r-- | arch/arm/mach-aaec2000/include/mach/debug-macro.S | 37 | ||||
-rw-r--r-- | arch/arm/mach-aaec2000/include/mach/dma.h | 9 | ||||
-rw-r--r-- | arch/arm/mach-aaec2000/include/mach/entry-macro.S | 40 | ||||
-rw-r--r-- | arch/arm/mach-aaec2000/include/mach/hardware.h | 50 | ||||
-rw-r--r-- | arch/arm/mach-aaec2000/include/mach/io.h | 20 | ||||
-rw-r--r-- | arch/arm/mach-aaec2000/include/mach/irqs.h | 46 | ||||
-rw-r--r-- | arch/arm/mach-aaec2000/include/mach/memory.h | 30 | ||||
-rw-r--r-- | arch/arm/mach-aaec2000/include/mach/system.h | 24 | ||||
-rw-r--r-- | arch/arm/mach-aaec2000/include/mach/timex.h | 18 | ||||
-rw-r--r-- | arch/arm/mach-aaec2000/include/mach/uncompress.h | 46 | ||||
-rw-r--r-- | arch/arm/mach-aaec2000/include/mach/vmalloc.h | 16 |
15 files changed, 586 insertions, 3 deletions
diff --git a/arch/arm/mach-aaec2000/aaed2000.c b/arch/arm/mach-aaec2000/aaed2000.c index 08f030d506b8..81a3ecc0d104 100644 --- a/arch/arm/mach-aaec2000/aaed2000.c +++ b/arch/arm/mach-aaec2000/aaed2000.c | |||
@@ -20,14 +20,14 @@ | |||
20 | #include <asm/setup.h> | 20 | #include <asm/setup.h> |
21 | #include <asm/memory.h> | 21 | #include <asm/memory.h> |
22 | #include <asm/mach-types.h> | 22 | #include <asm/mach-types.h> |
23 | #include <asm/arch/hardware.h> | 23 | #include <mach/hardware.h> |
24 | #include <asm/irq.h> | 24 | #include <asm/irq.h> |
25 | 25 | ||
26 | #include <asm/mach/arch.h> | 26 | #include <asm/mach/arch.h> |
27 | #include <asm/mach/map.h> | 27 | #include <asm/mach/map.h> |
28 | #include <asm/mach/irq.h> | 28 | #include <asm/mach/irq.h> |
29 | 29 | ||
30 | #include <asm/arch/aaed2000.h> | 30 | #include <mach/aaed2000.h> |
31 | 31 | ||
32 | #include "core.h" | 32 | #include "core.h" |
33 | 33 | ||
diff --git a/arch/arm/mach-aaec2000/core.c b/arch/arm/mach-aaec2000/core.c index 2e0cec2dc997..dfb26bc23d1a 100644 --- a/arch/arm/mach-aaec2000/core.c +++ b/arch/arm/mach-aaec2000/core.c | |||
@@ -20,7 +20,7 @@ | |||
20 | #include <linux/timex.h> | 20 | #include <linux/timex.h> |
21 | #include <linux/signal.h> | 21 | #include <linux/signal.h> |
22 | 22 | ||
23 | #include <asm/arch/hardware.h> | 23 | #include <mach/hardware.h> |
24 | #include <asm/irq.h> | 24 | #include <asm/irq.h> |
25 | #include <asm/sizes.h> | 25 | #include <asm/sizes.h> |
26 | 26 | ||
diff --git a/arch/arm/mach-aaec2000/include/mach/aaec2000.h b/arch/arm/mach-aaec2000/include/mach/aaec2000.h new file mode 100644 index 000000000000..bc729c42f843 --- /dev/null +++ b/arch/arm/mach-aaec2000/include/mach/aaec2000.h | |||
@@ -0,0 +1,207 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-aaec2000/include/mach/aaec2000.h | ||
3 | * | ||
4 | * AAEC-2000 registers definition | ||
5 | * | ||
6 | * Copyright (c) 2005 Nicolas Bellido Y Ortega | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_AAEC2000_H | ||
14 | #define __ASM_ARCH_AAEC2000_H | ||
15 | |||
16 | #ifndef __ASM_ARCH_HARDWARE_H | ||
17 | #error You must include hardware.h not this file | ||
18 | #endif /* __ASM_ARCH_HARDWARE_H */ | ||
19 | |||
20 | /* Chip selects */ | ||
21 | #define AAEC_CS0 0x00000000 | ||
22 | #define AAEC_CS1 0x10000000 | ||
23 | #define AAEC_CS2 0x20000000 | ||
24 | #define AAEC_CS3 0x30000000 | ||
25 | |||
26 | /* Flash */ | ||
27 | #define AAEC_FLASH_BASE AAEC_CS0 | ||
28 | #define AAEC_FLASH_SIZE SZ_64M | ||
29 | |||
30 | /* Interrupt controller */ | ||
31 | #define IRQ_BASE __REG(0x80000500) | ||
32 | #define IRQ_INTSR __REG(0x80000500) /* Int Status Register */ | ||
33 | #define IRQ_INTRSR __REG(0x80000504) /* Int Raw (unmasked) Status */ | ||
34 | #define IRQ_INTENS __REG(0x80000508) /* Int Enable Set */ | ||
35 | #define IRQ_INTENC __REG(0x8000050c) /* Int Enable Clear */ | ||
36 | |||
37 | /* UART 1 */ | ||
38 | #define UART1_BASE __REG(0x80000600) | ||
39 | #define UART1_DR __REG(0x80000600) /* Data/FIFO Register */ | ||
40 | #define UART1_LCR __REG(0x80000604) /* Link Control Register */ | ||
41 | #define UART1_BRCR __REG(0x80000608) /* Baud Rate Control Register */ | ||
42 | #define UART1_CR __REG(0x8000060c) /* Control Register */ | ||
43 | #define UART1_SR __REG(0x80000610) /* Status Register */ | ||
44 | #define UART1_INT __REG(0x80000614) /* Interrupt Status Register */ | ||
45 | #define UART1_INTM __REG(0x80000618) /* Interrupt Mask Register */ | ||
46 | #define UART1_INTRES __REG(0x8000061c) /* Int Result (masked status) Register */ | ||
47 | |||
48 | /* UART 2 */ | ||
49 | #define UART2_BASE __REG(0x80000700) | ||
50 | #define UART2_DR __REG(0x80000700) /* Data/FIFO Register */ | ||
51 | #define UART2_LCR __REG(0x80000704) /* Link Control Register */ | ||
52 | #define UART2_BRCR __REG(0x80000708) /* Baud Rate Control Register */ | ||
53 | #define UART2_CR __REG(0x8000070c) /* Control Register */ | ||
54 | #define UART2_SR __REG(0x80000710) /* Status Register */ | ||
55 | #define UART2_INT __REG(0x80000714) /* Interrupt Status Register */ | ||
56 | #define UART2_INTM __REG(0x80000718) /* Interrupt Mask Register */ | ||
57 | #define UART2_INTRES __REG(0x8000071c) /* Int Result (masked status) Register */ | ||
58 | |||
59 | /* UART 3 */ | ||
60 | #define UART3_BASE __REG(0x80000800) | ||
61 | #define UART3_DR __REG(0x80000800) /* Data/FIFO Register */ | ||
62 | #define UART3_LCR __REG(0x80000804) /* Link Control Register */ | ||
63 | #define UART3_BRCR __REG(0x80000808) /* Baud Rate Control Register */ | ||
64 | #define UART3_CR __REG(0x8000080c) /* Control Register */ | ||
65 | #define UART3_SR __REG(0x80000810) /* Status Register */ | ||
66 | #define UART3_INT __REG(0x80000814) /* Interrupt Status Register */ | ||
67 | #define UART3_INTM __REG(0x80000818) /* Interrupt Mask Register */ | ||
68 | #define UART3_INTRES __REG(0x8000081c) /* Int Result (masked status) Register */ | ||
69 | |||
70 | /* These are used in some places */ | ||
71 | #define _UART1_BASE __PREG(UART1_BASE) | ||
72 | #define _UART2_BASE __PREG(UART2_BASE) | ||
73 | #define _UART3_BASE __PREG(UART3_BASE) | ||
74 | |||
75 | /* UART Registers Offsets */ | ||
76 | #define UART_DR 0x00 | ||
77 | #define UART_LCR 0x04 | ||
78 | #define UART_BRCR 0x08 | ||
79 | #define UART_CR 0x0c | ||
80 | #define UART_SR 0x10 | ||
81 | #define UART_INT 0x14 | ||
82 | #define UART_INTM 0x18 | ||
83 | #define UART_INTRES 0x1c | ||
84 | |||
85 | /* UART_LCR Bitmask */ | ||
86 | #define UART_LCR_BRK (1 << 0) /* Send Break */ | ||
87 | #define UART_LCR_PEN (1 << 1) /* Parity Enable */ | ||
88 | #define UART_LCR_EP (1 << 2) /* Even/Odd Parity */ | ||
89 | #define UART_LCR_S2 (1 << 3) /* One/Two Stop bits */ | ||
90 | #define UART_LCR_FIFO (1 << 4) /* FIFO Enable */ | ||
91 | #define UART_LCR_WL5 (0 << 5) /* Word Length - 5 bits */ | ||
92 | #define UART_LCR_WL6 (1 << 5) /* Word Length - 6 bits */ | ||
93 | #define UART_LCR_WL7 (1 << 6) /* Word Length - 7 bits */ | ||
94 | #define UART_LCR_WL8 (1 << 7) /* Word Length - 8 bits */ | ||
95 | |||
96 | /* UART_CR Bitmask */ | ||
97 | #define UART_CR_EN (1 << 0) /* UART Enable */ | ||
98 | #define UART_CR_SIR (1 << 1) /* IrDA SIR Enable */ | ||
99 | #define UART_CR_SIRLP (1 << 2) /* Low Power IrDA Enable */ | ||
100 | #define UART_CR_RXP (1 << 3) /* Receive Pin Polarity */ | ||
101 | #define UART_CR_TXP (1 << 4) /* Transmit Pin Polarity */ | ||
102 | #define UART_CR_MXP (1 << 5) /* Modem Pin Polarity */ | ||
103 | #define UART_CR_LOOP (1 << 6) /* Loopback Mode */ | ||
104 | |||
105 | /* UART_SR Bitmask */ | ||
106 | #define UART_SR_CTS (1 << 0) /* Clear To Send Status */ | ||
107 | #define UART_SR_DSR (1 << 1) /* Data Set Ready Status */ | ||
108 | #define UART_SR_DCD (1 << 2) /* Data Carrier Detect Status */ | ||
109 | #define UART_SR_TxBSY (1 << 3) /* Transmitter Busy Status */ | ||
110 | #define UART_SR_RxFE (1 << 4) /* Receive FIFO Empty Status */ | ||
111 | #define UART_SR_TxFF (1 << 5) /* Transmit FIFO Full Status */ | ||
112 | #define UART_SR_RxFF (1 << 6) /* Receive FIFO Full Status */ | ||
113 | #define UART_SR_TxFE (1 << 7) /* Transmit FIFO Empty Status */ | ||
114 | |||
115 | /* UART_INT Bitmask */ | ||
116 | #define UART_INT_RIS (1 << 0) /* Rx Interrupt */ | ||
117 | #define UART_INT_TIS (1 << 1) /* Tx Interrupt */ | ||
118 | #define UART_INT_MIS (1 << 2) /* Modem Interrupt */ | ||
119 | #define UART_INT_RTIS (1 << 3) /* Receive Timeout Interrupt */ | ||
120 | |||
121 | /* Timer 1 */ | ||
122 | #define TIMER1_BASE __REG(0x80000c00) | ||
123 | #define TIMER1_LOAD __REG(0x80000c00) /* Timer 1 Load Register */ | ||
124 | #define TIMER1_VAL __REG(0x80000c04) /* Timer 1 Value Register */ | ||
125 | #define TIMER1_CTRL __REG(0x80000c08) /* Timer 1 Control Register */ | ||
126 | #define TIMER1_CLEAR __REG(0x80000c0c) /* Timer 1 Clear Register */ | ||
127 | |||
128 | /* Timer 2 */ | ||
129 | #define TIMER2_BASE __REG(0x80000d00) | ||
130 | #define TIMER2_LOAD __REG(0x80000d00) /* Timer 2 Load Register */ | ||
131 | #define TIMER2_VAL __REG(0x80000d04) /* Timer 2 Value Register */ | ||
132 | #define TIMER2_CTRL __REG(0x80000d08) /* Timer 2 Control Register */ | ||
133 | #define TIMER2_CLEAR __REG(0x80000d0c) /* Timer 2 Clear Register */ | ||
134 | |||
135 | /* Timer 3 */ | ||
136 | #define TIMER3_BASE __REG(0x80000e00) | ||
137 | #define TIMER3_LOAD __REG(0x80000e00) /* Timer 3 Load Register */ | ||
138 | #define TIMER3_VAL __REG(0x80000e04) /* Timer 3 Value Register */ | ||
139 | #define TIMER3_CTRL __REG(0x80000e08) /* Timer 3 Control Register */ | ||
140 | #define TIMER3_CLEAR __REG(0x80000e0c) /* Timer 3 Clear Register */ | ||
141 | |||
142 | /* Timer Control register bits */ | ||
143 | #define TIMER_CTRL_ENABLE (1 << 7) /* Enable (Start Timer) */ | ||
144 | #define TIMER_CTRL_PERIODIC (1 << 6) /* Periodic Running Mode */ | ||
145 | #define TIMER_CTRL_FREE_RUNNING (0 << 6) /* Normal Running Mode */ | ||
146 | #define TIMER_CTRL_CLKSEL_508K (1 << 3) /* 508KHz Clock select (Timer 1, 2) */ | ||
147 | #define TIMER_CTRL_CLKSEL_2K (0 << 3) /* 2KHz Clock Select (Timer 1, 2) */ | ||
148 | |||
149 | /* Power and State Control */ | ||
150 | #define POWER_BASE __REG(0x80000400) | ||
151 | #define POWER_PWRSR __REG(0x80000400) /* Power Status Register */ | ||
152 | #define POWER_PWRCNT __REG(0x80000404) /* Power/Clock control */ | ||
153 | #define POWER_HALT __REG(0x80000408) /* Power Idle Mode */ | ||
154 | #define POWER_STDBY __REG(0x8000040c) /* Power Standby Mode */ | ||
155 | #define POWER_BLEOI __REG(0x80000410) /* Battery Low End of Interrupt */ | ||
156 | #define POWER_MCEOI __REG(0x80000414) /* Media Changed EoI */ | ||
157 | #define POWER_TEOI __REG(0x80000418) /* Tick EoI */ | ||
158 | #define POWER_STFCLR __REG(0x8000041c) /* NbFlg, RSTFlg, PFFlg, CLDFlg Clear */ | ||
159 | #define POWER_CLKSET __REG(0x80000420) /* Clock Speed Control */ | ||
160 | |||
161 | /* GPIO Registers */ | ||
162 | #define AAEC_GPIO_PHYS 0x80000e00 | ||
163 | |||
164 | #define AAEC_GPIO_PADR __REG(AAEC_GPIO_PHYS + 0x00) | ||
165 | #define AAEC_GPIO_PBDR __REG(AAEC_GPIO_PHYS + 0x04) | ||
166 | #define AAEC_GPIO_PCDR __REG(AAEC_GPIO_PHYS + 0x08) | ||
167 | #define AAEC_GPIO_PDDR __REG(AAEC_GPIO_PHYS + 0x0c) | ||
168 | #define AAEC_GPIO_PADDR __REG(AAEC_GPIO_PHYS + 0x10) | ||
169 | #define AAEC_GPIO_PBDDR __REG(AAEC_GPIO_PHYS + 0x14) | ||
170 | #define AAEC_GPIO_PCDDR __REG(AAEC_GPIO_PHYS + 0x18) | ||
171 | #define AAEC_GPIO_PDDDR __REG(AAEC_GPIO_PHYS + 0x1c) | ||
172 | #define AAEC_GPIO_PEDR __REG(AAEC_GPIO_PHYS + 0x20) | ||
173 | #define AAEC_GPIO_PEDDR __REG(AAEC_GPIO_PHYS + 0x24) | ||
174 | #define AAEC_GPIO_KSCAN __REG(AAEC_GPIO_PHYS + 0x28) | ||
175 | #define AAEC_GPIO_PINMUX __REG(AAEC_GPIO_PHYS + 0x2c) | ||
176 | #define AAEC_GPIO_PFDR __REG(AAEC_GPIO_PHYS + 0x30) | ||
177 | #define AAEC_GPIO_PFDDR __REG(AAEC_GPIO_PHYS + 0x34) | ||
178 | #define AAEC_GPIO_PGDR __REG(AAEC_GPIO_PHYS + 0x38) | ||
179 | #define AAEC_GPIO_PGDDR __REG(AAEC_GPIO_PHYS + 0x3c) | ||
180 | #define AAEC_GPIO_PHDR __REG(AAEC_GPIO_PHYS + 0x40) | ||
181 | #define AAEC_GPIO_PHDDR __REG(AAEC_GPIO_PHYS + 0x44) | ||
182 | #define AAEC_GPIO_RAZ __REG(AAEC_GPIO_PHYS + 0x48) | ||
183 | #define AAEC_GPIO_INTTYPE1 __REG(AAEC_GPIO_PHYS + 0x4c) | ||
184 | #define AAEC_GPIO_INTTYPE2 __REG(AAEC_GPIO_PHYS + 0x50) | ||
185 | #define AAEC_GPIO_FEOI __REG(AAEC_GPIO_PHYS + 0x54) | ||
186 | #define AAEC_GPIO_INTEN __REG(AAEC_GPIO_PHYS + 0x58) | ||
187 | #define AAEC_GPIO_INTSTATUS __REG(AAEC_GPIO_PHYS + 0x5c) | ||
188 | #define AAEC_GPIO_RAWINTSTATUS __REG(AAEC_GPIO_PHYS + 0x60) | ||
189 | #define AAEC_GPIO_DB __REG(AAEC_GPIO_PHYS + 0x64) | ||
190 | #define AAEC_GPIO_PAPINDR __REG(AAEC_GPIO_PHYS + 0x68) | ||
191 | #define AAEC_GPIO_PBPINDR __REG(AAEC_GPIO_PHYS + 0x6c) | ||
192 | #define AAEC_GPIO_PCPINDR __REG(AAEC_GPIO_PHYS + 0x70) | ||
193 | #define AAEC_GPIO_PDPINDR __REG(AAEC_GPIO_PHYS + 0x74) | ||
194 | #define AAEC_GPIO_PEPINDR __REG(AAEC_GPIO_PHYS + 0x78) | ||
195 | #define AAEC_GPIO_PFPINDR __REG(AAEC_GPIO_PHYS + 0x7c) | ||
196 | #define AAEC_GPIO_PGPINDR __REG(AAEC_GPIO_PHYS + 0x80) | ||
197 | #define AAEC_GPIO_PHPINDR __REG(AAEC_GPIO_PHYS + 0x84) | ||
198 | |||
199 | #define AAEC_GPIO_PINMUX_PE0CON (1 << 0) | ||
200 | #define AAEC_GPIO_PINMUX_PD0CON (1 << 1) | ||
201 | #define AAEC_GPIO_PINMUX_CODECON (1 << 2) | ||
202 | #define AAEC_GPIO_PINMUX_UART3CON (1 << 3) | ||
203 | |||
204 | /* LCD Controller */ | ||
205 | #define AAEC_CLCD_PHYS 0x80003000 | ||
206 | |||
207 | #endif /* __ARM_ARCH_AAEC2000_H */ | ||
diff --git a/arch/arm/mach-aaec2000/include/mach/aaed2000.h b/arch/arm/mach-aaec2000/include/mach/aaed2000.h new file mode 100644 index 000000000000..f821295ca71b --- /dev/null +++ b/arch/arm/mach-aaec2000/include/mach/aaed2000.h | |||
@@ -0,0 +1,40 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-aaec2000/include/mach/aaed2000.h | ||
3 | * | ||
4 | * AAED-2000 specific bits definition | ||
5 | * | ||
6 | * Copyright (c) 2005 Nicolas Bellido Y Ortega | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_AAED2000_H | ||
14 | #define __ASM_ARCH_AAED2000_H | ||
15 | |||
16 | /* External GPIOs. */ | ||
17 | |||
18 | #define EXT_GPIO_PBASE AAEC_CS3 | ||
19 | #define EXT_GPIO_VBASE 0xf8100000 | ||
20 | #define EXT_GPIO_LENGTH 0x00001000 | ||
21 | |||
22 | #define __ext_gpio_p2v(x) ((x) - EXT_GPIO_PBASE + EXT_GPIO_VBASE) | ||
23 | #define __ext_gpio_v2p(x) ((x) + EXT_GPIO_PBASE - EXT_GPIO_VBASE) | ||
24 | |||
25 | #define __EXT_GPIO_REG(x) (*((volatile u32 *)__ext_gpio_p2v(x))) | ||
26 | #define __EXT_GPIO_PREG(x) (__ext_gpio_v2p((u32)&(x))) | ||
27 | |||
28 | #define AAED_EXT_GPIO __EXT_GPIO_REG(EXT_GPIO_PBASE) | ||
29 | |||
30 | #define AAED_EGPIO_KBD_SCAN 0x00003fff /* Keyboard scan data */ | ||
31 | #define AAED_EGPIO_PWR_INT 0x00008fff /* Smart battery charger interrupt */ | ||
32 | #define AAED_EGPIO_SWITCHED 0x000f0000 /* DIP Switches */ | ||
33 | #define AAED_EGPIO_USB_VBUS 0x00400000 /* USB Vbus sense */ | ||
34 | #define AAED_EGPIO_LCD_PWR_EN 0x02000000 /* LCD and backlight PWR enable */ | ||
35 | #define AAED_EGPIO_nLED0 0x20000000 /* LED 0 */ | ||
36 | #define AAED_EGPIO_nLED1 0x20000000 /* LED 1 */ | ||
37 | #define AAED_EGPIO_nLED2 0x20000000 /* LED 2 */ | ||
38 | |||
39 | |||
40 | #endif /* __ARM_ARCH_AAED2000_H */ | ||
diff --git a/arch/arm/mach-aaec2000/include/mach/debug-macro.S b/arch/arm/mach-aaec2000/include/mach/debug-macro.S new file mode 100644 index 000000000000..0b6351d7c389 --- /dev/null +++ b/arch/arm/mach-aaec2000/include/mach/debug-macro.S | |||
@@ -0,0 +1,37 @@ | |||
1 | /* arch/arm/mach-aaec2000/include/mach/debug-macro.S | ||
2 | * | ||
3 | * Debugging macro include header | ||
4 | * | ||
5 | * Copyright (c) 2005 Nicolas Bellido Y Ortega | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | |||
12 | #include "hardware.h" | ||
13 | .macro addruart,rx | ||
14 | mrc p15, 0, \rx, c1, c0 | ||
15 | tst \rx, #1 @ MMU enabled? | ||
16 | moveq \rx, #0x80000000 @ physical | ||
17 | movne \rx, #io_p2v(0x80000000) @ virtual | ||
18 | orr \rx, \rx, #0x00000800 | ||
19 | .endm | ||
20 | |||
21 | .macro senduart,rd,rx | ||
22 | str \rd, [\rx, #0] | ||
23 | .endm | ||
24 | |||
25 | .macro busyuart,rd,rx | ||
26 | 1002: ldr \rd, [\rx, #0x10] | ||
27 | tst \rd, #(1 << 7) | ||
28 | beq 1002b | ||
29 | .endm | ||
30 | |||
31 | .macro waituart,rd,rx | ||
32 | #if 0 | ||
33 | 1001: ldr \rd, [\rx, #0x10] | ||
34 | tst \rd, #(1 << 5) | ||
35 | beq 1001b | ||
36 | #endif | ||
37 | .endm | ||
diff --git a/arch/arm/mach-aaec2000/include/mach/dma.h b/arch/arm/mach-aaec2000/include/mach/dma.h new file mode 100644 index 000000000000..2da846c72fe7 --- /dev/null +++ b/arch/arm/mach-aaec2000/include/mach/dma.h | |||
@@ -0,0 +1,9 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-aaec2000/include/mach/dma.h | ||
3 | * | ||
4 | * Copyright (c) 2005 Nicolas Bellido Y Ortega | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
diff --git a/arch/arm/mach-aaec2000/include/mach/entry-macro.S b/arch/arm/mach-aaec2000/include/mach/entry-macro.S new file mode 100644 index 000000000000..c8fb34469007 --- /dev/null +++ b/arch/arm/mach-aaec2000/include/mach/entry-macro.S | |||
@@ -0,0 +1,40 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-aaec2000/include/mach/entry-macro.S | ||
3 | * | ||
4 | * Low-level IRQ helper for aaec-2000 based platforms | ||
5 | * | ||
6 | * Copyright (c) 2005 Nicolas Bellido Y Ortega | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | * | ||
12 | */ | ||
13 | #include <mach/irqs.h> | ||
14 | |||
15 | .macro disable_fiq | ||
16 | .endm | ||
17 | |||
18 | .macro get_irqnr_preamble, base, tmp | ||
19 | .endm | ||
20 | |||
21 | .macro arch_ret_to_user, tmp1, tmp2 | ||
22 | .endm | ||
23 | |||
24 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
25 | mov r4, #0xf8000000 | ||
26 | add r4, r4, #0x00000500 | ||
27 | mov \base, r4 | ||
28 | ldr \irqstat, [\base, #0] | ||
29 | cmp \irqstat, #0 | ||
30 | bne 1001f | ||
31 | ldr \irqnr, =NR_IRQS+1 | ||
32 | b 1003f | ||
33 | 1001: mov \irqnr, #0 | ||
34 | 1002: ands \tmp, \irqstat, #1 | ||
35 | mov \irqstat, \irqstat, LSR #1 | ||
36 | add \irqnr, \irqnr, #1 | ||
37 | beq 1002b | ||
38 | sub \irqnr, \irqnr, #1 | ||
39 | 1003: | ||
40 | .endm | ||
diff --git a/arch/arm/mach-aaec2000/include/mach/hardware.h b/arch/arm/mach-aaec2000/include/mach/hardware.h new file mode 100644 index 000000000000..965a6f6672d6 --- /dev/null +++ b/arch/arm/mach-aaec2000/include/mach/hardware.h | |||
@@ -0,0 +1,50 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-aaec2000/include/mach/hardware.h | ||
3 | * | ||
4 | * Copyright (c) 2005 Nicolas Bellido Y Ortega | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_ARCH_HARDWARE_H | ||
12 | #define __ASM_ARCH_HARDWARE_H | ||
13 | |||
14 | #include <asm/sizes.h> | ||
15 | #include <mach/aaec2000.h> | ||
16 | |||
17 | /* The kernel is loaded at physical address 0xf8000000. | ||
18 | * We map the IO space a bit after | ||
19 | */ | ||
20 | #define PIO_APB_BASE 0x80000000 | ||
21 | #define VIO_APB_BASE 0xf8000000 | ||
22 | #define IO_APB_LENGTH 0x2000 | ||
23 | #define PIO_AHB_BASE 0x80002000 | ||
24 | #define VIO_AHB_BASE 0xf8002000 | ||
25 | #define IO_AHB_LENGTH 0x2000 | ||
26 | |||
27 | #define VIO_BASE VIO_APB_BASE | ||
28 | #define PIO_BASE PIO_APB_BASE | ||
29 | |||
30 | #define io_p2v(x) ( (x) - PIO_BASE + VIO_BASE ) | ||
31 | #define io_v2p(x) ( (x) + PIO_BASE - VIO_BASE ) | ||
32 | |||
33 | #ifndef __ASSEMBLY__ | ||
34 | |||
35 | #include <asm/types.h> | ||
36 | |||
37 | /* FIXME: Is it needed to optimize this a la pxa ?? */ | ||
38 | #define __REG(x) (*((volatile u32 *)io_p2v(x))) | ||
39 | #define __PREG(x) (io_v2p((u32)&(x))) | ||
40 | |||
41 | #else /* __ASSEMBLY__ */ | ||
42 | |||
43 | #define __REG(x) io_p2v(x) | ||
44 | #define __PREG(x) io_v2p(x) | ||
45 | |||
46 | #endif | ||
47 | |||
48 | #include "aaec2000.h" | ||
49 | |||
50 | #endif /* __ASM_ARCH_HARDWARE_H */ | ||
diff --git a/arch/arm/mach-aaec2000/include/mach/io.h b/arch/arm/mach-aaec2000/include/mach/io.h new file mode 100644 index 000000000000..c87c24de1110 --- /dev/null +++ b/arch/arm/mach-aaec2000/include/mach/io.h | |||
@@ -0,0 +1,20 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-aaec2000/include/mach/io.h | ||
3 | * | ||
4 | * Copied from asm/arch/sa1100/io.h | ||
5 | */ | ||
6 | #ifndef __ASM_ARM_ARCH_IO_H | ||
7 | #define __ASM_ARM_ARCH_IO_H | ||
8 | |||
9 | #include <mach/hardware.h> | ||
10 | |||
11 | #define IO_SPACE_LIMIT 0xffffffff | ||
12 | |||
13 | /* | ||
14 | * We don't actually have real ISA nor PCI buses, but there is so many | ||
15 | * drivers out there that might just work if we fake them... | ||
16 | */ | ||
17 | #define __io(a) ((void __iomem *)(a)) | ||
18 | #define __mem_pci(a) (a) | ||
19 | |||
20 | #endif | ||
diff --git a/arch/arm/mach-aaec2000/include/mach/irqs.h b/arch/arm/mach-aaec2000/include/mach/irqs.h new file mode 100644 index 000000000000..bf45c6d2f294 --- /dev/null +++ b/arch/arm/mach-aaec2000/include/mach/irqs.h | |||
@@ -0,0 +1,46 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-aaec2000/include/mach/irqs.h | ||
3 | * | ||
4 | * Copyright (c) 2005 Nicolas Bellido Y Ortega | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_ARCH_IRQS_H | ||
12 | #define __ASM_ARCH_IRQS_H | ||
13 | |||
14 | |||
15 | #define INT_GPIOF0_FIQ 0 /* External GPIO Port F O Fast Interrupt Input */ | ||
16 | #define INT_BL_FIQ 1 /* Battery Low Fast Interrupt */ | ||
17 | #define INT_WE_FIQ 2 /* Watchdog Expired Fast Interrupt */ | ||
18 | #define INT_MV_FIQ 3 /* Media Changed Interrupt */ | ||
19 | #define INT_SC 4 /* Sound Codec Interrupt */ | ||
20 | #define INT_GPIO1 5 /* GPIO Port F Configurable Int 1 */ | ||
21 | #define INT_GPIO2 6 /* GPIO Port F Configurable Int 2 */ | ||
22 | #define INT_GPIO3 7 /* GPIO Port F Configurable Int 3 */ | ||
23 | #define INT_TMR1_OFL 8 /* Timer 1 Overflow Interrupt */ | ||
24 | #define INT_TMR2_OFL 9 /* Timer 2 Overflow Interrupt */ | ||
25 | #define INT_RTC_CM 10 /* RTC Compare Match Interrupt */ | ||
26 | #define INT_TICK 11 /* 64Hz Tick Interrupt */ | ||
27 | #define INT_UART1 12 /* UART1 Interrupt */ | ||
28 | #define INT_UART2 13 /* UART2 & Modem State Changed Interrupt */ | ||
29 | #define INT_LCD 14 /* LCD Interrupt */ | ||
30 | #define INT_SSI 15 /* SSI End of Transfer Interrupt */ | ||
31 | #define INT_UART3 16 /* UART3 Interrupt */ | ||
32 | #define INT_SCI 17 /* SCI Interrupt */ | ||
33 | #define INT_AAC 18 /* Advanced Audio Codec Interrupt */ | ||
34 | #define INT_MMC 19 /* MMC Interrupt */ | ||
35 | #define INT_USB 20 /* USB Interrupt */ | ||
36 | #define INT_DMA 21 /* DMA Interrupt */ | ||
37 | #define INT_TMR3_UOFL 22 /* Timer 3 Underflow Interrupt */ | ||
38 | #define INT_GPIO4 23 /* GPIO Port F Configurable Int 4 */ | ||
39 | #define INT_GPIO5 24 /* GPIO Port F Configurable Int 4 */ | ||
40 | #define INT_GPIO6 25 /* GPIO Port F Configurable Int 4 */ | ||
41 | #define INT_GPIO7 26 /* GPIO Port F Configurable Int 4 */ | ||
42 | #define INT_BMI 27 /* BMI Interrupt */ | ||
43 | |||
44 | #define NR_IRQS (INT_BMI + 1) | ||
45 | |||
46 | #endif /* __ASM_ARCH_IRQS_H */ | ||
diff --git a/arch/arm/mach-aaec2000/include/mach/memory.h b/arch/arm/mach-aaec2000/include/mach/memory.h new file mode 100644 index 000000000000..56ae900a482e --- /dev/null +++ b/arch/arm/mach-aaec2000/include/mach/memory.h | |||
@@ -0,0 +1,30 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-aaec2000/include/mach/memory.h | ||
3 | * | ||
4 | * Copyright (c) 2005 Nicolas Bellido Y Ortega | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_ARCH_MEMORY_H | ||
12 | #define __ASM_ARCH_MEMORY_H | ||
13 | |||
14 | |||
15 | #define PHYS_OFFSET UL(0xf0000000) | ||
16 | |||
17 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
18 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
19 | |||
20 | /* | ||
21 | * The nodes are the followings: | ||
22 | * | ||
23 | * node 0: 0xf000.0000 - 0xf3ff.ffff | ||
24 | * node 1: 0xf400.0000 - 0xf7ff.ffff | ||
25 | * node 2: 0xf800.0000 - 0xfbff.ffff | ||
26 | * node 3: 0xfc00.0000 - 0xffff.ffff | ||
27 | */ | ||
28 | #define NODE_MEM_SIZE_BITS 26 | ||
29 | |||
30 | #endif /* __ASM_ARCH_MEMORY_H */ | ||
diff --git a/arch/arm/mach-aaec2000/include/mach/system.h b/arch/arm/mach-aaec2000/include/mach/system.h new file mode 100644 index 000000000000..8f4115d734ce --- /dev/null +++ b/arch/arm/mach-aaec2000/include/mach/system.h | |||
@@ -0,0 +1,24 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-aaed2000/include/mach/system.h | ||
3 | * | ||
4 | * Copyright (c) 2005 Nicolas Bellido Y Ortega | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_ARCH_SYSTEM_H | ||
12 | #define __ASM_ARCH_SYSTEM_H | ||
13 | |||
14 | static inline void arch_idle(void) | ||
15 | { | ||
16 | cpu_do_idle(); | ||
17 | } | ||
18 | |||
19 | static inline void arch_reset(char mode) | ||
20 | { | ||
21 | cpu_reset(0); | ||
22 | } | ||
23 | |||
24 | #endif /* __ASM_ARCH_SYSTEM_H */ | ||
diff --git a/arch/arm/mach-aaec2000/include/mach/timex.h b/arch/arm/mach-aaec2000/include/mach/timex.h new file mode 100644 index 000000000000..6c8edf4a8828 --- /dev/null +++ b/arch/arm/mach-aaec2000/include/mach/timex.h | |||
@@ -0,0 +1,18 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-aaec2000/include/mach/timex.h | ||
3 | * | ||
4 | * AAEC-2000 Architecture timex specification | ||
5 | * | ||
6 | * Copyright (c) 2005 Nicolas Bellido Y Ortega | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_TIMEX_H | ||
14 | #define __ASM_ARCH_TIMEX_H | ||
15 | |||
16 | #define CLOCK_TICK_RATE 508000 | ||
17 | |||
18 | #endif /* __ASM_ARCH_TIMEX_H */ | ||
diff --git a/arch/arm/mach-aaec2000/include/mach/uncompress.h b/arch/arm/mach-aaec2000/include/mach/uncompress.h new file mode 100644 index 000000000000..381ecad1a1bb --- /dev/null +++ b/arch/arm/mach-aaec2000/include/mach/uncompress.h | |||
@@ -0,0 +1,46 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-aaec2000/include/mach/uncompress.h | ||
3 | * | ||
4 | * Copyright (c) 2005 Nicolas Bellido Y Ortega | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_ARCH_UNCOMPRESS_H | ||
12 | #define __ASM_ARCH_UNCOMPRESS_H | ||
13 | |||
14 | #include "hardware.h" | ||
15 | |||
16 | #define UART(x) (*(volatile unsigned long *)(serial_port + (x))) | ||
17 | |||
18 | static void putc(int c) | ||
19 | { | ||
20 | unsigned long serial_port; | ||
21 | do { | ||
22 | serial_port = _UART3_BASE; | ||
23 | if (UART(UART_CR) & UART_CR_EN) break; | ||
24 | serial_port = _UART1_BASE; | ||
25 | if (UART(UART_CR) & UART_CR_EN) break; | ||
26 | serial_port = _UART2_BASE; | ||
27 | if (UART(UART_CR) & UART_CR_EN) break; | ||
28 | return; | ||
29 | } while (0); | ||
30 | |||
31 | /* wait for space in the UART's transmitter */ | ||
32 | while ((UART(UART_SR) & UART_SR_TxFF)) | ||
33 | barrier(); | ||
34 | |||
35 | /* send the character out. */ | ||
36 | UART(UART_DR) = c; | ||
37 | } | ||
38 | |||
39 | static inline void flush(void) | ||
40 | { | ||
41 | } | ||
42 | |||
43 | #define arch_decomp_setup() | ||
44 | #define arch_decomp_wdog() | ||
45 | |||
46 | #endif /* __ASM_ARCH_UNCOMPRESS_H */ | ||
diff --git a/arch/arm/mach-aaec2000/include/mach/vmalloc.h b/arch/arm/mach-aaec2000/include/mach/vmalloc.h new file mode 100644 index 000000000000..551f68f666bf --- /dev/null +++ b/arch/arm/mach-aaec2000/include/mach/vmalloc.h | |||
@@ -0,0 +1,16 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-aaec2000/include/mach/vmalloc.h | ||
3 | * | ||
4 | * Copyright (c) 2005 Nicolas Bellido Y Ortega | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_ARCH_VMALLOC_H | ||
12 | #define __ASM_ARCH_VMALLOC_H | ||
13 | |||
14 | #define VMALLOC_END (PAGE_OFFSET + 0x10000000) | ||
15 | |||
16 | #endif /* __ASM_ARCH_VMALLOC_H */ | ||