diff options
author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-06-26 18:01:05 -0400 |
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committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-06-26 18:01:05 -0400 |
commit | f6e6e883730aff2718610d3eba7608fcf73328ed (patch) | |
tree | ec595db5e2454ac5f505a2ce971e45d674f8d6b3 /arch/arm/lib/io-writesw-armv3.S | |
parent | ba262e4a4d4c23b5e6c15dbb3a99696b562e8035 (diff) | |
parent | f964c303fe33b0d2ee563349bc8bea4d57d7a265 (diff) |
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm:
[ARM] 3657/1: S3C24XX: Documentation update of Overview.txt
[ARM] Update mach-types
[ARM] 3656/1: S3C2412: Add S3C2412 and S3C2413 documenation
[ARM] 3654/1: add ajeco 1arm sbc support
[ARM] fix drivers/mfd/ucb1x00-core.c IRQ probing bug
[ARM] 3651/1: S3C24XX: Make arch list more detailed
[ARM] 3650/1: S3C2412: Update s3c2410_defconfig
[ARM] 3649/1: S3C24XX: Fix capitalisation of CPU on SMDK2440
[ARM] 3612/1: make pci bus optional for ixp4xx platform
[ARM] Remove MODE_(SVC|IRQ|FIQ|USR) and DEFAULT_FIQ
[ARM] Remove save_lr/restore_pc macros
[ARM] Remove partial non-v6 binutils compatibility
[ARM] Remove LOADREGS macro
[ARM] Remove RETINSTR macro
Diffstat (limited to 'arch/arm/lib/io-writesw-armv3.S')
-rw-r--r-- | arch/arm/lib/io-writesw-armv3.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/lib/io-writesw-armv3.S b/arch/arm/lib/io-writesw-armv3.S index 52d62b481295..1607a29f49b7 100644 --- a/arch/arm/lib/io-writesw-armv3.S +++ b/arch/arm/lib/io-writesw-armv3.S | |||
@@ -29,7 +29,7 @@ | |||
29 | orr r3, r3, r3, lsl #16 | 29 | orr r3, r3, r3, lsl #16 |
30 | str r3, [r0] | 30 | str r3, [r0] |
31 | subs r2, r2, #1 | 31 | subs r2, r2, #1 |
32 | RETINSTR(moveq, pc, lr) | 32 | moveq pc, lr |
33 | 33 | ||
34 | ENTRY(__raw_writesw) | 34 | ENTRY(__raw_writesw) |
35 | teq r2, #0 @ do we have to check for the zero len? | 35 | teq r2, #0 @ do we have to check for the zero len? |
@@ -80,7 +80,7 @@ ENTRY(__raw_writesw) | |||
80 | bpl .Loutsw_8_lp | 80 | bpl .Loutsw_8_lp |
81 | 81 | ||
82 | tst r2, #7 | 82 | tst r2, #7 |
83 | LOADREGS(eqfd, sp!, {r4, r5, r6, pc}) | 83 | ldmeqfd sp!, {r4, r5, r6, pc} |
84 | 84 | ||
85 | .Lno_outsw_8: tst r2, #4 | 85 | .Lno_outsw_8: tst r2, #4 |
86 | beq .Lno_outsw_4 | 86 | beq .Lno_outsw_4 |
@@ -124,4 +124,4 @@ ENTRY(__raw_writesw) | |||
124 | orrne ip, ip, ip, lsr #16 | 124 | orrne ip, ip, ip, lsr #16 |
125 | strne ip, [r0] | 125 | strne ip, [r0] |
126 | 126 | ||
127 | LOADREGS(fd, sp!, {r4, r5, r6, pc}) | 127 | ldmfd sp!, {r4, r5, r6, pc} |