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| author | Linus Torvalds <torvalds@g5.osdl.org> | 2005-11-11 19:30:35 -0500 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2005-11-11 19:30:35 -0500 |
| commit | 9cf93d7b2f4516271ccf5b48f958bd474cf9dd67 (patch) | |
| tree | e743282bdf6b808cc7739c614fc7158609470ace /arch/arm/lib/io-readsw-armv3.S | |
| parent | 401221501af4b87b502eca36ece97b4191380082 (diff) | |
| parent | c6bd2328434a3a6f8f6bc6f77f49c12ec966448a (diff) | |
Merge master.kernel.org:/home/rmk/linux-2.6-arm
Diffstat (limited to 'arch/arm/lib/io-readsw-armv3.S')
| -rw-r--r-- | arch/arm/lib/io-readsw-armv3.S | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/arch/arm/lib/io-readsw-armv3.S b/arch/arm/lib/io-readsw-armv3.S index 476cf7f8a633..146d47c15455 100644 --- a/arch/arm/lib/io-readsw-armv3.S +++ b/arch/arm/lib/io-readsw-armv3.S | |||
| @@ -11,16 +11,16 @@ | |||
| 11 | #include <asm/assembler.h> | 11 | #include <asm/assembler.h> |
| 12 | #include <asm/hardware.h> | 12 | #include <asm/hardware.h> |
| 13 | 13 | ||
| 14 | .insw_bad_alignment: | 14 | .Linsw_bad_alignment: |
| 15 | adr r0, .insw_bad_align_msg | 15 | adr r0, .Linsw_bad_align_msg |
| 16 | mov r2, lr | 16 | mov r2, lr |
| 17 | b panic | 17 | b panic |
| 18 | .insw_bad_align_msg: | 18 | .Linsw_bad_align_msg: |
| 19 | .asciz "insw: bad buffer alignment (0x%p, lr=0x%08lX)\n" | 19 | .asciz "insw: bad buffer alignment (0x%p, lr=0x%08lX)\n" |
| 20 | .align | 20 | .align |
| 21 | 21 | ||
| 22 | .insw_align: tst r1, #1 | 22 | .Linsw_align: tst r1, #1 |
| 23 | bne .insw_bad_alignment | 23 | bne .Linsw_bad_alignment |
| 24 | 24 | ||
| 25 | ldr r3, [r0] | 25 | ldr r3, [r0] |
| 26 | strb r3, [r1], #1 | 26 | strb r3, [r1], #1 |
| @@ -34,16 +34,16 @@ ENTRY(__raw_readsw) | |||
| 34 | teq r2, #0 @ do we have to check for the zero len? | 34 | teq r2, #0 @ do we have to check for the zero len? |
| 35 | moveq pc, lr | 35 | moveq pc, lr |
| 36 | tst r1, #3 | 36 | tst r1, #3 |
| 37 | bne .insw_align | 37 | bne .Linsw_align |
| 38 | 38 | ||
| 39 | .insw_aligned: mov ip, #0xff | 39 | .Linsw_aligned: mov ip, #0xff |
| 40 | orr ip, ip, ip, lsl #8 | 40 | orr ip, ip, ip, lsl #8 |
| 41 | stmfd sp!, {r4, r5, r6, lr} | 41 | stmfd sp!, {r4, r5, r6, lr} |
| 42 | 42 | ||
| 43 | subs r2, r2, #8 | 43 | subs r2, r2, #8 |
| 44 | bmi .no_insw_8 | 44 | bmi .Lno_insw_8 |
| 45 | 45 | ||
| 46 | .insw_8_lp: ldr r3, [r0] | 46 | .Linsw_8_lp: ldr r3, [r0] |
| 47 | and r3, r3, ip | 47 | and r3, r3, ip |
| 48 | ldr r4, [r0] | 48 | ldr r4, [r0] |
| 49 | orr r3, r3, r4, lsl #16 | 49 | orr r3, r3, r4, lsl #16 |
| @@ -66,13 +66,13 @@ ENTRY(__raw_readsw) | |||
| 66 | stmia r1!, {r3 - r6} | 66 | stmia r1!, {r3 - r6} |
| 67 | 67 | ||
| 68 | subs r2, r2, #8 | 68 | subs r2, r2, #8 |
| 69 | bpl .insw_8_lp | 69 | bpl .Linsw_8_lp |
| 70 | 70 | ||
| 71 | tst r2, #7 | 71 | tst r2, #7 |
| 72 | LOADREGS(eqfd, sp!, {r4, r5, r6, pc}) | 72 | LOADREGS(eqfd, sp!, {r4, r5, r6, pc}) |
| 73 | 73 | ||
| 74 | .no_insw_8: tst r2, #4 | 74 | .Lno_insw_8: tst r2, #4 |
| 75 | beq .no_insw_4 | 75 | beq .Lno_insw_4 |
| 76 | 76 | ||
| 77 | ldr r3, [r0] | 77 | ldr r3, [r0] |
| 78 | and r3, r3, ip | 78 | and r3, r3, ip |
| @@ -86,8 +86,8 @@ ENTRY(__raw_readsw) | |||
| 86 | 86 | ||
| 87 | stmia r1!, {r3, r4} | 87 | stmia r1!, {r3, r4} |
| 88 | 88 | ||
| 89 | .no_insw_4: tst r2, #2 | 89 | .Lno_insw_4: tst r2, #2 |
| 90 | beq .no_insw_2 | 90 | beq .Lno_insw_2 |
| 91 | 91 | ||
| 92 | ldr r3, [r0] | 92 | ldr r3, [r0] |
| 93 | and r3, r3, ip | 93 | and r3, r3, ip |
| @@ -96,7 +96,7 @@ ENTRY(__raw_readsw) | |||
| 96 | 96 | ||
| 97 | str r3, [r1], #4 | 97 | str r3, [r1], #4 |
| 98 | 98 | ||
| 99 | .no_insw_2: tst r2, #1 | 99 | .Lno_insw_2: tst r2, #1 |
| 100 | ldrne r3, [r0] | 100 | ldrne r3, [r0] |
| 101 | strneb r3, [r1], #1 | 101 | strneb r3, [r1], #1 |
| 102 | movne r3, r3, lsr #8 | 102 | movne r3, r3, lsr #8 |