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author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-04-03 19:15:17 -0400 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-04-03 19:15:17 -0400 |
commit | 66ade474237745a57b7e87da9a93c7ec69fd52bb (patch) | |
tree | a3e08728d8584fde056ec51f4b2249e3dd6032c5 /arch/arm/lib/delay.c | |
parent | cbfa0e7204159515e63321142bcc2d6dcb854045 (diff) | |
parent | 4e1db26a0b42e2b6e27c05d68adcc01709c2eed2 (diff) |
Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm
Pull ARM fixes from Russell King:
"Another round of ARM fixes, which include:
- Fixing a problem with LPAE mapping sections
- Reporting of some hwcaps on Krait CPUs
- Avoiding repetitive warnings in the breakpoint code
- Fixing a build error noticed on Dove platforms with PJ4 CPUs
- Fix masking of level 2 cache revision.
- Fixing timer-based udelay()
- A larger fix for an erratum causing people major grief with Cortex
A15 CPUs"
* 'fixes' of git://git.linaro.org/people/rmk/linux-arm:
ARM: 7690/1: mm: fix CONFIG_LPAE typos
ARM: 7689/1: add unwind annotations to ftrace asm
ARM: 7685/1: delay: use private ticks_per_jiffy field for timer-based delay ops
ARM: 7684/1: errata: Workaround for Cortex-A15 erratum 798181 (TLBI/DSB operations)
ARM: 7682/1: cache-l2x0: fix masking of RTL revision numbering and set_debug init
ARM: iWMMXt: always enable iWMMXt support with PJ4 CPUs
ARM: 7681/1: hw_breakpoint: use warn_once to avoid spam from reset_ctrl_regs()
ARM: 7678/1: Work around faulty ISAR0 register in some Krait CPUs
ARM: 7680/1: Detect support for SDIV/UDIV from ISAR0 register
ARM: 7679/1: Clear IDIVT hwcap if CONFIG_ARM_THUMB=n
ARM: 7677/1: LPAE: Fix mapping in alloc_init_section for unaligned addresses
ARM: KVM: vgic: take distributor lock on sync_hwstate path
ARM: KVM: vgic: force EOIed LRs to the empty state
Diffstat (limited to 'arch/arm/lib/delay.c')
-rw-r--r-- | arch/arm/lib/delay.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/arch/arm/lib/delay.c b/arch/arm/lib/delay.c index 6b93f6a1a3c7..64dbfa57204a 100644 --- a/arch/arm/lib/delay.c +++ b/arch/arm/lib/delay.c | |||
@@ -58,7 +58,7 @@ static void __timer_delay(unsigned long cycles) | |||
58 | static void __timer_const_udelay(unsigned long xloops) | 58 | static void __timer_const_udelay(unsigned long xloops) |
59 | { | 59 | { |
60 | unsigned long long loops = xloops; | 60 | unsigned long long loops = xloops; |
61 | loops *= loops_per_jiffy; | 61 | loops *= arm_delay_ops.ticks_per_jiffy; |
62 | __timer_delay(loops >> UDELAY_SHIFT); | 62 | __timer_delay(loops >> UDELAY_SHIFT); |
63 | } | 63 | } |
64 | 64 | ||
@@ -73,11 +73,13 @@ void __init register_current_timer_delay(const struct delay_timer *timer) | |||
73 | pr_info("Switching to timer-based delay loop\n"); | 73 | pr_info("Switching to timer-based delay loop\n"); |
74 | delay_timer = timer; | 74 | delay_timer = timer; |
75 | lpj_fine = timer->freq / HZ; | 75 | lpj_fine = timer->freq / HZ; |
76 | loops_per_jiffy = lpj_fine; | 76 | |
77 | /* cpufreq may scale loops_per_jiffy, so keep a private copy */ | ||
78 | arm_delay_ops.ticks_per_jiffy = lpj_fine; | ||
77 | arm_delay_ops.delay = __timer_delay; | 79 | arm_delay_ops.delay = __timer_delay; |
78 | arm_delay_ops.const_udelay = __timer_const_udelay; | 80 | arm_delay_ops.const_udelay = __timer_const_udelay; |
79 | arm_delay_ops.udelay = __timer_udelay; | 81 | arm_delay_ops.udelay = __timer_udelay; |
80 | arm_delay_ops.const_clock = true; | 82 | |
81 | delay_calibrated = true; | 83 | delay_calibrated = true; |
82 | } else { | 84 | } else { |
83 | pr_info("Ignoring duplicate/late registration of read_current_timer delay\n"); | 85 | pr_info("Ignoring duplicate/late registration of read_current_timer delay\n"); |