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authorCatalin Marinas <catalin.marinas@arm.com>2006-01-12 11:53:51 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-01-12 11:53:51 -0500
commit90303b102353302e84758f245906368907e6a23b (patch)
tree3e417666985ee5875c2d3435518de2c4bdc9b88d /arch/arm/lib/csumpartialcopy.S
parentece5f7b3c4fde70a1ae4add7372ebca5c90bc34d (diff)
[ARM] 3256/1: Make the function-returning ldm's use sp as the base register
Patch from Catalin Marinas If the low interrupt latency mode is enabled for the CPU (from ARMv6 onwards), the ldm/stm instructions are no longer atomic. An ldm instruction restoring the sp and pc registers can be interrupted immediately after sp was updated but before the pc. If this happens, the CPU restores the base register to the value before the ldm instruction but if the base register is not sp, the interrupt routine will corrupt the stack and the restarted ldm instruction will load garbage. Note that future ARM cores might always run in the low interrupt latency mode. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/lib/csumpartialcopy.S')
-rw-r--r--arch/arm/lib/csumpartialcopy.S6
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/lib/csumpartialcopy.S b/arch/arm/lib/csumpartialcopy.S
index 990ee63b2465..21effe0dbf97 100644
--- a/arch/arm/lib/csumpartialcopy.S
+++ b/arch/arm/lib/csumpartialcopy.S
@@ -18,11 +18,13 @@
18 */ 18 */
19 19
20 .macro save_regs 20 .macro save_regs
21 mov ip, sp
21 stmfd sp!, {r1, r4 - r8, fp, ip, lr, pc} 22 stmfd sp!, {r1, r4 - r8, fp, ip, lr, pc}
23 sub fp, ip, #4
22 .endm 24 .endm
23 25
24 .macro load_regs,flags 26 .macro load_regs
25 LOADREGS(\flags,fp,{r1, r4 - r8, fp, sp, pc}) 27 ldmfd sp, {r1, r4 - r8, fp, sp, pc}
26 .endm 28 .endm
27 29
28 .macro load1b, reg1 30 .macro load1b, reg1