ARM: Remove support for ARMv3 ARM610 and ARM710 CPUs

This patch removes support for ARMv3 CPUs, which haven't worked properly
for quite some time (see the FIXME comment in arch/arm/mm/fault.c).  The
only V3 parts left is the cache model for ARMv3, which is needed for some
odd reason by ARM740T CPUs, and being able to build with -march=armv3,
which is required for the RiscPC platform due to its bus structure.

Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

2 files changed, 0 insertions, 32 deletions

diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 7fd3ad048da9..437f0c426517 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -556,10 +556,6 @@ call_fpe:
 #endif
         tst     r0, #0x08000000                 @ only CDP/CPRT/LDC/STC have bit 27
         tstne   r0, #0x04000000                 @ bit 26 set on both ARM and Thumb-2
-#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
-        and     r8, r0, #0x0f000000             @ mask out op-code bits
-        teqne   r8, #0x0f000000                 @ SWI (ARM6/7 bug)?
-#endif
         moveq   pc, lr
         get_thread_info r10                     @ get current thread
         and     r8, r0, #0x00000f00             @ mask out CP number
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 54ee265dd819..7bd2d3cb8957 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -335,20 +335,6 @@ ENDPROC(ftrace_stub)
  *-----------------------------------------------------------------------------
  */
 
-        /* If we're optimising for StrongARM the resulting code won't 
-           run on an ARM7 and we can save a couple of instructions.  
-                                                                --pb */
-#ifdef CONFIG_CPU_ARM710
-#define A710(code...) code
-.Larm710bug:
-        ldmia   sp, {r0 - lr}^                  @ Get calling r0 - lr
-        mov     r0, r0
-        add     sp, sp, #S_FRAME_SIZE
-        subs    pc, lr, #4
-#else
-#define A710(code...)
-#endif
-
         .align  5
 ENTRY(vector_swi)
         sub     sp, sp, #S_FRAME_SIZE
@@ -379,9 +365,6 @@ ENTRY(vector_swi)
         ldreq   r10, [lr, #-4]                  @ get SWI instruction
 #else
         ldr     r10, [lr, #-4]                  @ get SWI instruction
-  A710( and     ip, r10, #0x0f000000            @ check for SWI         )
-  A710( teq     ip, #0x0f000000                                         )
-  A710( bne     .Larm710bug                                             )
 #endif
 #ifdef CONFIG_CPU_ENDIAN_BE8
         rev     r10, r10                        @ little endian instruction
@@ -392,26 +375,15 @@ ENTRY(vector_swi)
         /*
          * Pure EABI user space always put syscall number into scno (r7).
          */
-  A710( ldr     ip, [lr, #-4]                   @ get SWI instruction   )
-  A710( and     ip, ip, #0x0f000000             @ check for SWI         )
-  A710( teq     ip, #0x0f000000                                         )
-  A710( bne     .Larm710bug                                             )
-
 #elif defined(CONFIG_ARM_THUMB)
-
         /* Legacy ABI only, possibly thumb mode. */
         tst     r8, #PSR_T_BIT                  @ this is SPSR from save_user_regs
         addne   scno, r7, #__NR_SYSCALL_BASE    @ put OS number in
         ldreq   scno, [lr, #-4]
 
 #else
-
         /* Legacy ABI only. */
         ldr     scno, [lr, #-4]                 @ get SWI instruction
-  A710( and     ip, scno, #0x0f000000           @ check for SWI         )
-  A710( teq     ip, #0x0f000000                                         )
-  A710( bne     .Larm710bug                                             )
-
 #endif
 
 #ifdef CONFIG_ALIGNMENT_TRAP