ARM: 6826/1: Merge v6 and v7 DEBUG_LL DCC support

The inline assembly differences for v6 vs. v7 are purely
optimizations. On a v7 processor, an mrc with the pc sets the
condition codes to the 28-31 bits of the register being read. It
just so happens that the TX/RX full bits the DCC support code is
testing for are high enough in the register to be put into the
condition codes. On a v6 processor, this "feature" isn't
implemented and thus we have to do the usual read, mask, test
operations to check for TX/RX full. Thus, we can drop the v7
implementation and just use the v6 implementation for both.

Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 1 insertions, 18 deletions

diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S
index d2d983be096d..bcd66e00bdbe 100644
--- a/arch/arm/kernel/debug.S
+++ b/arch/arm/kernel/debug.S
@@ -25,7 +25,7 @@
                 .macro  addruart, rp, rv
                 .endm
 
-#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
+#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
 
                 .macro  senduart, rd, rx
                 mcr     p14, 0, \rd, c0, c5, 0
@@ -49,23 +49,6 @@
 1002:
                 .endm
 
-#elif defined(CONFIG_CPU_V7)
-
-                .macro  senduart, rd, rx
-                mcr     p14, 0, \rd, c0, c5, 0
-                .endm
-
-                .macro  busyuart, rd, rx
-busy:           mrc     p14, 0, pc, c0, c1, 0
-                bcs     busy
-                .endm
-
-                .macro  waituart, rd, rx
-wait:           mrc     p14, 0, pc, c0, c1, 0
-                bcs     wait
-
-                .endm
-
 #elif defined(CONFIG_CPU_XSCALE)
 
                 .macro  senduart, rd, rx