diff options
author | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-01-04 14:39:29 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-02-17 18:27:33 -0500 |
commit | cada3c0841e1deaec4c0f92654610b028dc683ff (patch) | |
tree | 9c6085c8b8447795ddc749315a31fd3906a6159d /arch/arm/kernel | |
parent | dc21af99fadcfa0ae65b52fd0895f85824f0c288 (diff) |
ARM: P2V: extend to 16-bit translation offsets
MSM's memory is aligned to 2MB, which is more than we can do with our
existing method as we're limited to the upper 8 bits. Extend this by
using two instructions to 16 bits, automatically selected when MSM is
enabled.
Acked-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Tested-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/kernel')
-rw-r--r-- | arch/arm/kernel/head.S | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 1db8ead2e331..a94dd99d54c3 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S | |||
@@ -456,8 +456,13 @@ __fixup_pv_table: | |||
456 | add r4, r4, r3 @ adjust table start address | 456 | add r4, r4, r3 @ adjust table start address |
457 | add r5, r5, r3 @ adjust table end address | 457 | add r5, r5, r3 @ adjust table end address |
458 | str r8, [r7, r3]! @ save computed PHYS_OFFSET to __pv_phys_offset | 458 | str r8, [r7, r3]! @ save computed PHYS_OFFSET to __pv_phys_offset |
459 | #ifndef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT | ||
459 | mov r6, r3, lsr #24 @ constant for add/sub instructions | 460 | mov r6, r3, lsr #24 @ constant for add/sub instructions |
460 | teq r3, r6, lsl #24 @ must be 16MiB aligned | 461 | teq r3, r6, lsl #24 @ must be 16MiB aligned |
462 | #else | ||
463 | mov r6, r3, lsr #16 @ constant for add/sub instructions | ||
464 | teq r3, r6, lsl #16 @ must be 64kiB aligned | ||
465 | #endif | ||
461 | bne __error | 466 | bne __error |
462 | str r6, [r7, #4] @ save to __pv_offset | 467 | str r6, [r7, #4] @ save to __pv_offset |
463 | b __fixup_a_pv_table | 468 | b __fixup_a_pv_table |
@@ -471,10 +476,18 @@ ENDPROC(__fixup_pv_table) | |||
471 | 476 | ||
472 | .text | 477 | .text |
473 | __fixup_a_pv_table: | 478 | __fixup_a_pv_table: |
479 | #ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT | ||
480 | and r0, r6, #255 @ offset bits 23-16 | ||
481 | mov r6, r6, lsr #8 @ offset bits 31-24 | ||
482 | #else | ||
483 | mov r0, #0 @ just in case... | ||
484 | #endif | ||
474 | b 3f | 485 | b 3f |
475 | 2: ldr ip, [r7, r3] | 486 | 2: ldr ip, [r7, r3] |
476 | bic ip, ip, #0x000000ff | 487 | bic ip, ip, #0x000000ff |
477 | orr ip, ip, r6 | 488 | tst ip, #0x400 @ rotate shift tells us LS or MS byte |
489 | orrne ip, ip, r6 @ mask in offset bits 31-24 | ||
490 | orreq ip, ip, r0 @ mask in offset bits 23-16 | ||
478 | str ip, [r7, r3] | 491 | str ip, [r7, r3] |
479 | 3: cmp r4, r5 | 492 | 3: cmp r4, r5 |
480 | ldrcc r7, [r4], #4 @ use branch for delay slot | 493 | ldrcc r7, [r4], #4 @ use branch for delay slot |