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authorWill Deacon <will.deacon@arm.com>2011-03-25 08:12:23 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-03-26 06:06:09 -0400
commitd25d3b4c4d0e27975ee659a64b6d29f02fdbfde4 (patch)
tree649a912d82c53b372389eea0e4ea29f3a85bf201 /arch/arm/kernel
parentfb4fe87d79511398a68000d2100c825f54b51652 (diff)
ARM: 6833/1: perf: add required isbs() to ARMv7 backend
The ARMv7 architecture does not guarantee that effects from co-processor writes are immediately visible to following instructions. This patch adds two isbs to the ARMv7 perf code: (1) Immediately after selecting an event register, so that the PMU state following this instruction is consistent with the new event. (2) Immediately before writing to the PMCR, so that any previous writes to the PMU have taken effect before (typically) enabling the counters. Acked-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/kernel')
-rw-r--r--arch/arm/kernel/perf_event_v7.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index 2e1402556fa0..d6c9dcd1979f 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -466,6 +466,7 @@ static inline unsigned long armv7_pmnc_read(void)
466static inline void armv7_pmnc_write(unsigned long val) 466static inline void armv7_pmnc_write(unsigned long val)
467{ 467{
468 val &= ARMV7_PMNC_MASK; 468 val &= ARMV7_PMNC_MASK;
469 isb();
469 asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val)); 470 asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val));
470} 471}
471 472
@@ -502,6 +503,7 @@ static inline int armv7_pmnc_select_counter(unsigned int idx)
502 503
503 val = (idx - ARMV7_EVENT_CNT_TO_CNTx) & ARMV7_SELECT_MASK; 504 val = (idx - ARMV7_EVENT_CNT_TO_CNTx) & ARMV7_SELECT_MASK;
504 asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val)); 505 asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val));
506 isb();
505 507
506 return idx; 508 return idx;
507} 509}