ARM: LPAE: add ISBs around MMU enabling code

Before we enable the MMU, we must ensure that the TTBR registers contain
sane values. After the MMU has been enabled, we jump to the *virtual*
address of the following function, so we also need to ensure that the
SCTLR write has taken effect.

This patch adds ISB instructions around the SCTLR write to ensure the
visibility of the above.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

2 files changed, 4 insertions, 0 deletions

diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 64e9943ea4f0..54eb94aff6cd 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -401,8 +401,10 @@ ENDPROC(__enable_mmu)
         .pushsection    .idmap.text, "ax"
 ENTRY(__turn_mmu_on)
         mov     r0, r0
+        instr_sync
         mcr     p15, 0, r0, c1, c0, 0           @ write control reg
         mrc     p15, 0, r3, c0, c0, 0           @ read id reg
+        instr_sync
         mov     r3, r3
         mov     r3, r13
         mov     pc, r3
diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index 9e64231c8cfe..1f268bda4552 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -57,8 +57,10 @@ ENDPROC(cpu_suspend_abort)
         .pushsection    .idmap.text,"ax"
 ENTRY(cpu_resume_mmu)
         ldr     r3, =cpu_resume_after_mmu
+        instr_sync
         mcr     p15, 0, r0, c1, c0, 0   @ turn on MMU, I-cache, etc
         mrc     p15, 0, r0, c0, c0, 0   @ read id reg
+        instr_sync
         mov     r0, r0
         mov     r0, r0
         mov     pc, r3                  @ jump to virtual address