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authorWill Deacon <will.deacon@arm.com>2011-10-07 10:57:55 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-10-08 05:05:34 -0400
commita26bce1220a4c5a7a074a779e6aad3cae63a94f7 (patch)
treeb57a67eab4799e63e7fc699acd7682b8148ebbb8 /arch/arm/kernel
parentc825dda905bac330c2da7fabdf5c0ac28758b3cd (diff)
ARM: 7127/1: hw_breakpoint: skip v7-specific reset on v6 cores
ARMv6 cores do not implement the DBGOSLAR register, so we don't need to try and clear it on boot. Furthermore, the VCR is zeroed out of reset, so we don't need to zero it explicitly when a CPU comes online. Tested-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/kernel')
-rw-r--r--arch/arm/kernel/hw_breakpoint.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index 5a46225f007e..814a52a9dc39 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -892,6 +892,10 @@ static void reset_ctrl_regs(void *unused)
892 * later on. 892 * later on.
893 */ 893 */
894 switch (debug_arch) { 894 switch (debug_arch) {
895 case ARM_DEBUG_ARCH_V6:
896 case ARM_DEBUG_ARCH_V6_1:
897 /* ARMv6 cores just need to reset the registers. */
898 goto reset_regs;
895 case ARM_DEBUG_ARCH_V7_ECP14: 899 case ARM_DEBUG_ARCH_V7_ECP14:
896 /* 900 /*
897 * Ensure sticky power-down is clear (i.e. debug logic is 901 * Ensure sticky power-down is clear (i.e. debug logic is
@@ -931,6 +935,7 @@ static void reset_ctrl_regs(void *unused)
931 asm volatile("mcr p14, 0, %0, c0, c7, 0" : : "r" (0)); 935 asm volatile("mcr p14, 0, %0, c0, c7, 0" : : "r" (0));
932 isb(); 936 isb();
933 937
938reset_regs:
934 if (enable_monitor_mode()) 939 if (enable_monitor_mode())
935 return; 940 return;
936 941