aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/kernel/sleep.S
diff options
context:
space:
mode:
authorLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2014-05-08 12:31:40 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2014-05-25 18:49:27 -0400
commit0e0779da2233f2dfc85e9c3a6ea142476d326811 (patch)
tree8222330d72936e63a8cec7d45956cb669bed6d14 /arch/arm/kernel/sleep.S
parent72e6ae285a1dbff553734985bedadf409d99c02d (diff)
ARM: 8053/1: kernel: sleep: restore HYP mode configuration in cpu_resume
On CPUs with virtualization extensions the kernel installs HYP mode configuration on both primary and secondary cpus upon cold boot. On platforms where CPUs are shutdown in idle paths (ie CPU core gating), when a CPU resumes from low-power states it currently does not execute code that reinstalls the HYP configuration, which means that the kernel cannot run eg KVM properly on such machines. This patch, mirroring cold-boot behaviour, executes position independent code that reinstalls HYP configuration and drops to SVC mode safely on warmboot, so that deep idle states can be enabled in kernel running as hosts on platforms with power management HW. Cc: Christoffer Dall <christoffer.dall@linaro.org> Cc: Dave Martin <dave.martin@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Nicolas Pitre <nico@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Dave Martin <Dave.Martin@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/kernel/sleep.S')
-rw-r--r--arch/arm/kernel/sleep.S5
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index b907d9b790ab..1b880db2a033 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -127,6 +127,10 @@ ENDPROC(cpu_resume_after_mmu)
127 .align 127 .align
128ENTRY(cpu_resume) 128ENTRY(cpu_resume)
129ARM_BE8(setend be) @ ensure we are in BE mode 129ARM_BE8(setend be) @ ensure we are in BE mode
130#ifdef CONFIG_ARM_VIRT_EXT
131 bl __hyp_stub_install_secondary
132#endif
133 safe_svcmode_maskall r1
130 mov r1, #0 134 mov r1, #0
131 ALT_SMP(mrc p15, 0, r0, c0, c0, 5) 135 ALT_SMP(mrc p15, 0, r0, c0, c0, 5)
132 ALT_UP_B(1f) 136 ALT_UP_B(1f)
@@ -144,7 +148,6 @@ ARM_BE8(setend be) @ ensure we are in BE mode
144 ldr r0, [r0, #SLEEP_SAVE_SP_PHYS] 148 ldr r0, [r0, #SLEEP_SAVE_SP_PHYS]
145 ldr r0, [r0, r1, lsl #2] 149 ldr r0, [r0, r1, lsl #2]
146 150
147 setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set SVC, irqs off
148 @ load phys pgd, stack, resume fn 151 @ load phys pgd, stack, resume fn
149 ARM( ldmia r0!, {r1, sp, pc} ) 152 ARM( ldmia r0!, {r1, sp, pc} )
150THUMB( ldmia r0!, {r1, r2, r3} ) 153THUMB( ldmia r0!, {r1, r2, r3} )