diff options
author | Will Deacon <will.deacon@arm.com> | 2011-06-03 12:40:15 -0400 |
---|---|---|
committer | Will Deacon <will.deacon@arm.com> | 2011-07-07 14:20:53 -0400 |
commit | 0c205cbe20654616e2f8389c0c1ff707d9dccb63 (patch) | |
tree | bff2cc25f48b911faac970f5c0b98b6a795509e9 /arch/arm/kernel/perf_event_v7.c | |
parent | 6d4eaf991c654af54a19c0fa48e0ad62cefbc37c (diff) |
ARM: perf: add support for the Cortex-A5 PMU
This patch adds support for the Cortex-A5 PMU to the ARMv7 perf-event
backend.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm/kernel/perf_event_v7.c')
-rw-r--r-- | arch/arm/kernel/perf_event_v7.c | 146 |
1 files changed, 146 insertions, 0 deletions
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c index 01b1145f07e5..db1d6c4a32ac 100644 --- a/arch/arm/kernel/perf_event_v7.c +++ b/arch/arm/kernel/perf_event_v7.c | |||
@@ -153,6 +153,21 @@ enum armv7_a9_perf_types { | |||
153 | ARMV7_PERFCTR_PLE_RQST_PROG = 0xA5 | 153 | ARMV7_PERFCTR_PLE_RQST_PROG = 0xA5 |
154 | }; | 154 | }; |
155 | 155 | ||
156 | /* ARMv7 Cortex-A5 specific event types */ | ||
157 | enum armv7_a5_perf_types { | ||
158 | ARMV7_PERFCTR_IRQ_TAKEN = 0x86, | ||
159 | ARMV7_PERFCTR_FIQ_TAKEN = 0x87, | ||
160 | |||
161 | ARMV7_PERFCTR_EXT_MEM_RQST = 0xc0, | ||
162 | ARMV7_PERFCTR_NC_EXT_MEM_RQST = 0xc1, | ||
163 | ARMV7_PERFCTR_PREFETCH_LINEFILL = 0xc2, | ||
164 | ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP = 0xc3, | ||
165 | ARMV7_PERFCTR_ENTER_READ_ALLOC = 0xc4, | ||
166 | ARMV7_PERFCTR_READ_ALLOC = 0xc5, | ||
167 | |||
168 | ARMV7_PERFCTR_STALL_SB_FULL = 0xc9, | ||
169 | }; | ||
170 | |||
156 | /* | 171 | /* |
157 | * Cortex-A8 HW events mapping | 172 | * Cortex-A8 HW events mapping |
158 | * | 173 | * |
@@ -379,6 +394,122 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | |||
379 | }; | 394 | }; |
380 | 395 | ||
381 | /* | 396 | /* |
397 | * Cortex-A5 HW events mapping | ||
398 | */ | ||
399 | static const unsigned armv7_a5_perf_map[PERF_COUNT_HW_MAX] = { | ||
400 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, | ||
401 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, | ||
402 | [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, | ||
403 | [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, | ||
404 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, | ||
405 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, | ||
406 | [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED, | ||
407 | }; | ||
408 | |||
409 | static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | ||
410 | [PERF_COUNT_HW_CACHE_OP_MAX] | ||
411 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { | ||
412 | [C(L1D)] = { | ||
413 | [C(OP_READ)] = { | ||
414 | [C(RESULT_ACCESS)] | ||
415 | = ARMV7_PERFCTR_DCACHE_ACCESS, | ||
416 | [C(RESULT_MISS)] | ||
417 | = ARMV7_PERFCTR_DCACHE_REFILL, | ||
418 | }, | ||
419 | [C(OP_WRITE)] = { | ||
420 | [C(RESULT_ACCESS)] | ||
421 | = ARMV7_PERFCTR_DCACHE_ACCESS, | ||
422 | [C(RESULT_MISS)] | ||
423 | = ARMV7_PERFCTR_DCACHE_REFILL, | ||
424 | }, | ||
425 | [C(OP_PREFETCH)] = { | ||
426 | [C(RESULT_ACCESS)] | ||
427 | = ARMV7_PERFCTR_PREFETCH_LINEFILL, | ||
428 | [C(RESULT_MISS)] | ||
429 | = ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP, | ||
430 | }, | ||
431 | }, | ||
432 | [C(L1I)] = { | ||
433 | [C(OP_READ)] = { | ||
434 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, | ||
435 | [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS, | ||
436 | }, | ||
437 | [C(OP_WRITE)] = { | ||
438 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, | ||
439 | [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS, | ||
440 | }, | ||
441 | /* | ||
442 | * The prefetch counters don't differentiate between the I | ||
443 | * side and the D side. | ||
444 | */ | ||
445 | [C(OP_PREFETCH)] = { | ||
446 | [C(RESULT_ACCESS)] | ||
447 | = ARMV7_PERFCTR_PREFETCH_LINEFILL, | ||
448 | [C(RESULT_MISS)] | ||
449 | = ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP, | ||
450 | }, | ||
451 | }, | ||
452 | [C(LL)] = { | ||
453 | [C(OP_READ)] = { | ||
454 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
455 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
456 | }, | ||
457 | [C(OP_WRITE)] = { | ||
458 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
459 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
460 | }, | ||
461 | [C(OP_PREFETCH)] = { | ||
462 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
463 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
464 | }, | ||
465 | }, | ||
466 | [C(DTLB)] = { | ||
467 | [C(OP_READ)] = { | ||
468 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
469 | [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, | ||
470 | }, | ||
471 | [C(OP_WRITE)] = { | ||
472 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
473 | [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, | ||
474 | }, | ||
475 | [C(OP_PREFETCH)] = { | ||
476 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
477 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
478 | }, | ||
479 | }, | ||
480 | [C(ITLB)] = { | ||
481 | [C(OP_READ)] = { | ||
482 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
483 | [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS, | ||
484 | }, | ||
485 | [C(OP_WRITE)] = { | ||
486 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
487 | [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS, | ||
488 | }, | ||
489 | [C(OP_PREFETCH)] = { | ||
490 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
491 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
492 | }, | ||
493 | }, | ||
494 | [C(BPU)] = { | ||
495 | [C(OP_READ)] = { | ||
496 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, | ||
497 | [C(RESULT_MISS)] | ||
498 | = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, | ||
499 | }, | ||
500 | [C(OP_WRITE)] = { | ||
501 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, | ||
502 | [C(RESULT_MISS)] | ||
503 | = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, | ||
504 | }, | ||
505 | [C(OP_PREFETCH)] = { | ||
506 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
507 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
508 | }, | ||
509 | }, | ||
510 | }; | ||
511 | |||
512 | /* | ||
382 | * Perf Events counters | 513 | * Perf Events counters |
383 | */ | 514 | */ |
384 | enum armv7_counters { | 515 | enum armv7_counters { |
@@ -910,6 +1041,16 @@ static const struct arm_pmu *__init armv7_a9_pmu_init(void) | |||
910 | armv7pmu.num_events = armv7_read_num_pmnc_events(); | 1041 | armv7pmu.num_events = armv7_read_num_pmnc_events(); |
911 | return &armv7pmu; | 1042 | return &armv7pmu; |
912 | } | 1043 | } |
1044 | |||
1045 | static const struct arm_pmu *__init armv7_a5_pmu_init(void) | ||
1046 | { | ||
1047 | armv7pmu.id = ARM_PERF_PMU_ID_CA5; | ||
1048 | armv7pmu.name = "ARMv7 Cortex-A5"; | ||
1049 | armv7pmu.cache_map = &armv7_a5_perf_cache_map; | ||
1050 | armv7pmu.event_map = &armv7_a5_perf_map; | ||
1051 | armv7pmu.num_events = armv7_read_num_pmnc_events(); | ||
1052 | return &armv7pmu; | ||
1053 | } | ||
913 | #else | 1054 | #else |
914 | static const struct arm_pmu *__init armv7_a8_pmu_init(void) | 1055 | static const struct arm_pmu *__init armv7_a8_pmu_init(void) |
915 | { | 1056 | { |
@@ -920,4 +1061,9 @@ static const struct arm_pmu *__init armv7_a9_pmu_init(void) | |||
920 | { | 1061 | { |
921 | return NULL; | 1062 | return NULL; |
922 | } | 1063 | } |
1064 | |||
1065 | static const struct arm_pmu *__init armv7_a5_pmu_init(void) | ||
1066 | { | ||
1067 | return NULL; | ||
1068 | } | ||
923 | #endif /* CONFIG_CPU_V7 */ | 1069 | #endif /* CONFIG_CPU_V7 */ |