ARM: 6521/1: perf: use raw_spinlock_t for pmu_lock

For kernels built with PREEMPT_RT, critical sections protected
by standard spinlocks are preemptible. This is not acceptable
on perf as (a) we may be scheduled onto a different CPU whilst
reading/writing banked PMU registers and (b) the latency when
reading the PMU registers becomes unpredictable.

This patch upgrades the pmu_lock spinlock to a raw_spinlock
instead.

Reported-by: Jamie Iles <jamie@jamieiles.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 10 insertions, 10 deletions

diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c
index 3f427aae211d..c058bfc8532b 100644
--- a/arch/arm/kernel/perf_event_v6.c
+++ b/arch/arm/kernel/perf_event_v6.c
@@ -426,12 +426,12 @@ armv6pmu_enable_event(struct hw_perf_event *hwc,
          * Mask out the current event and set the counter to count the event
          * that we're interested in.
          */
-        spin_lock_irqsave(&pmu_lock, flags);
+        raw_spin_lock_irqsave(&pmu_lock, flags);
         val = armv6_pmcr_read();
         val &= ~mask;
         val |= evt;
         armv6_pmcr_write(val);
-        spin_unlock_irqrestore(&pmu_lock, flags);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
 }
 
 static irqreturn_t
@@ -500,11 +500,11 @@ armv6pmu_start(void)
 {
         unsigned long flags, val;
 
-        spin_lock_irqsave(&pmu_lock, flags);
+        raw_spin_lock_irqsave(&pmu_lock, flags);
         val = armv6_pmcr_read();
         val |= ARMV6_PMCR_ENABLE;
         armv6_pmcr_write(val);
-        spin_unlock_irqrestore(&pmu_lock, flags);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
 }
 
 static void
@@ -512,11 +512,11 @@ armv6pmu_stop(void)
 {
         unsigned long flags, val;
 
-        spin_lock_irqsave(&pmu_lock, flags);
+        raw_spin_lock_irqsave(&pmu_lock, flags);
         val = armv6_pmcr_read();
         val &= ~ARMV6_PMCR_ENABLE;
         armv6_pmcr_write(val);
-        spin_unlock_irqrestore(&pmu_lock, flags);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
 }
 
 static int
@@ -570,12 +570,12 @@ armv6pmu_disable_event(struct hw_perf_event *hwc,
          * of ETM bus signal assertion cycles. The external reporting should
          * be disabled and so this should never increment.
          */
-        spin_lock_irqsave(&pmu_lock, flags);
+        raw_spin_lock_irqsave(&pmu_lock, flags);
         val = armv6_pmcr_read();
         val &= ~mask;
         val |= evt;
         armv6_pmcr_write(val);
-        spin_unlock_irqrestore(&pmu_lock, flags);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
 }
 
 static void
@@ -599,12 +599,12 @@ armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc,
          * Unlike UP ARMv6, we don't have a way of stopping the counters. We
          * simply disable the interrupt reporting.
          */
-        spin_lock_irqsave(&pmu_lock, flags);
+        raw_spin_lock_irqsave(&pmu_lock, flags);
         val = armv6_pmcr_read();
         val &= ~mask;
         val |= evt;
         armv6_pmcr_write(val);
-        spin_unlock_irqrestore(&pmu_lock, flags);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
 }
 
 static const struct arm_pmu armv6pmu = {