diff options
author | Jon Medhurst <tixy@yxit.co.uk> | 2011-06-10 13:32:15 -0400 |
---|---|---|
committer | Tixy <tixy@medhuaa1.miniserver.com> | 2011-07-13 13:32:50 -0400 |
commit | 12ce5d3388dab15109e94eb847c948b23b709a03 (patch) | |
tree | 9bd9a9eb4bc8dd3190a9fd40316fb9bdc4598dd3 /arch/arm/kernel/kprobes-arm.c | |
parent | c82584ebdf5948bfc6f0509be1c2bef714b49a33 (diff) |
ARM: kprobes: Add emulate_rdlo12rdhi16rn0rm8_rwflags_nopc()
This is the emulation function for the instruction format used by the
ARM multiply long instructions. It replaces use of
prep_emulate_rdhi16rdlo12rs8rm0_wflags().
Signed-off-by: Jon Medhurst <tixy@yxit.co.uk>
Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Diffstat (limited to 'arch/arm/kernel/kprobes-arm.c')
-rw-r--r-- | arch/arm/kernel/kprobes-arm.c | 39 |
1 files changed, 36 insertions, 3 deletions
diff --git a/arch/arm/kernel/kprobes-arm.c b/arch/arm/kernel/kprobes-arm.c index 688101f2d39a..bb38ae3601c8 100644 --- a/arch/arm/kernel/kprobes-arm.c +++ b/arch/arm/kernel/kprobes-arm.c | |||
@@ -1033,6 +1033,36 @@ emulate_rd12rm0_noflags_nopc(struct kprobe *p, struct pt_regs *regs) | |||
1033 | regs->uregs[rd] = rdv; | 1033 | regs->uregs[rd] = rdv; |
1034 | } | 1034 | } |
1035 | 1035 | ||
1036 | static void __kprobes | ||
1037 | emulate_rdlo12rdhi16rn0rm8_rwflags_nopc(struct kprobe *p, struct pt_regs *regs) | ||
1038 | { | ||
1039 | kprobe_opcode_t insn = p->opcode; | ||
1040 | int rdlo = (insn >> 12) & 0xf; | ||
1041 | int rdhi = (insn >> 16) & 0xf; | ||
1042 | int rn = insn & 0xf; | ||
1043 | int rm = (insn >> 8) & 0xf; | ||
1044 | |||
1045 | register unsigned long rdlov asm("r0") = regs->uregs[rdlo]; | ||
1046 | register unsigned long rdhiv asm("r2") = regs->uregs[rdhi]; | ||
1047 | register unsigned long rnv asm("r3") = regs->uregs[rn]; | ||
1048 | register unsigned long rmv asm("r1") = regs->uregs[rm]; | ||
1049 | unsigned long cpsr = regs->ARM_cpsr; | ||
1050 | |||
1051 | __asm__ __volatile__ ( | ||
1052 | "msr cpsr_fs, %[cpsr] \n\t" | ||
1053 | BLX("%[fn]") | ||
1054 | "mrs %[cpsr], cpsr \n\t" | ||
1055 | : "=r" (rdlov), "=r" (rdhiv), [cpsr] "=r" (cpsr) | ||
1056 | : "0" (rdlov), "1" (rdhiv), "r" (rnv), "r" (rmv), | ||
1057 | "2" (cpsr), [fn] "r" (p->ainsn.insn_fn) | ||
1058 | : "lr", "memory", "cc" | ||
1059 | ); | ||
1060 | |||
1061 | regs->uregs[rdlo] = rdlov; | ||
1062 | regs->uregs[rdhi] = rdhiv; | ||
1063 | regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK); | ||
1064 | } | ||
1065 | |||
1036 | /* | 1066 | /* |
1037 | * For the instruction masking and comparisons in all the "space_*" | 1067 | * For the instruction masking and comparisons in all the "space_*" |
1038 | * functions below, Do _not_ rearrange the order of tests unless | 1068 | * functions below, Do _not_ rearrange the order of tests unless |
@@ -1111,7 +1141,8 @@ static const union decode_item arm_cccc_0001_0xx0____1xx0_table[] = { | |||
1111 | /* Halfword multiply and multiply-accumulate */ | 1141 | /* Halfword multiply and multiply-accumulate */ |
1112 | 1142 | ||
1113 | /* SMLALxy cccc 0001 0100 xxxx xxxx xxxx 1xx0 xxxx */ | 1143 | /* SMLALxy cccc 0001 0100 xxxx xxxx xxxx 1xx0 xxxx */ |
1114 | DECODE_CUSTOM (0x0ff00090, 0x01400080, prep_emulate_rdhi16rdlo12rs8rm0_wflags), | 1144 | DECODE_EMULATEX (0x0ff00090, 0x01400080, emulate_rdlo12rdhi16rn0rm8_rwflags_nopc, |
1145 | REGS(NOPC, NOPC, NOPC, 0, NOPC)), | ||
1115 | 1146 | ||
1116 | /* SMULWy cccc 0001 0010 xxxx xxxx xxxx 1x10 xxxx */ | 1147 | /* SMULWy cccc 0001 0010 xxxx xxxx xxxx 1x10 xxxx */ |
1117 | DECODE_OR (0x0ff000b0, 0x012000a0), | 1148 | DECODE_OR (0x0ff000b0, 0x012000a0), |
@@ -1153,7 +1184,8 @@ static const union decode_item arm_cccc_0000_____1001_table[] = { | |||
1153 | /* SMULLS cccc 0000 1101 xxxx xxxx xxxx 1001 xxxx */ | 1184 | /* SMULLS cccc 0000 1101 xxxx xxxx xxxx 1001 xxxx */ |
1154 | /* SMLAL cccc 0000 1110 xxxx xxxx xxxx 1001 xxxx */ | 1185 | /* SMLAL cccc 0000 1110 xxxx xxxx xxxx 1001 xxxx */ |
1155 | /* SMLALS cccc 0000 1111 xxxx xxxx xxxx 1001 xxxx */ | 1186 | /* SMLALS cccc 0000 1111 xxxx xxxx xxxx 1001 xxxx */ |
1156 | DECODE_CUSTOM (0x0f8000f0, 0x00800090, prep_emulate_rdhi16rdlo12rs8rm0_wflags), | 1187 | DECODE_EMULATEX (0x0f8000f0, 0x00800090, emulate_rdlo12rdhi16rn0rm8_rwflags_nopc, |
1188 | REGS(NOPC, NOPC, NOPC, 0, NOPC)), | ||
1157 | 1189 | ||
1158 | DECODE_END | 1190 | DECODE_END |
1159 | }; | 1191 | }; |
@@ -1422,7 +1454,8 @@ static const union decode_item arm_cccc_0111_____xxx1_table[] = { | |||
1422 | 1454 | ||
1423 | /* SMLALD cccc 0111 0100 xxxx xxxx xxxx 00x1 xxxx */ | 1455 | /* SMLALD cccc 0111 0100 xxxx xxxx xxxx 00x1 xxxx */ |
1424 | /* SMLSLD cccc 0111 0100 xxxx xxxx xxxx 01x1 xxxx */ | 1456 | /* SMLSLD cccc 0111 0100 xxxx xxxx xxxx 01x1 xxxx */ |
1425 | DECODE_CUSTOM (0x0ff00090, 0x07400010, prep_emulate_rdhi16rdlo12rs8rm0_wflags), | 1457 | DECODE_EMULATEX (0x0ff00090, 0x07400010, emulate_rdlo12rdhi16rn0rm8_rwflags_nopc, |
1458 | REGS(NOPC, NOPC, NOPC, 0, NOPC)), | ||
1426 | 1459 | ||
1427 | /* SMUAD cccc 0111 0000 xxxx 1111 xxxx 00x1 xxxx */ | 1460 | /* SMUAD cccc 0111 0000 xxxx 1111 xxxx 00x1 xxxx */ |
1428 | /* SMUSD cccc 0111 0000 xxxx 1111 xxxx 01x1 xxxx */ | 1461 | /* SMUSD cccc 0111 0000 xxxx 1111 xxxx 01x1 xxxx */ |