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author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-07-02 18:04:12 -0400 |
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committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-07-02 18:04:12 -0400 |
commit | a8c4c20dfa8b28a3c99e33c639d9c2ea5657741e (patch) | |
tree | 887b64d29b5a46d9ab2ca1267d8a2f05b5845561 /arch/arm/kernel/iwmmxt-notifier.c | |
parent | 168d04b3b4de7723eb73b3cffc9cb75224e0f393 (diff) | |
parent | 2dc7667b9d0674db6572723356fe3857031101a4 (diff) |
Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (44 commits)
[ARM] 3541/2: workaround for PXA27x erratum E7
[ARM] nommu: provide a way for correct control register value selection
[ARM] 3705/1: add supersection support to ioremap()
[ARM] 3707/1: iwmmxt: use the generic thread notifier infrastructure
[ARM] 3706/2: ep93xx: add cirrus logic edb9315a support
[ARM] 3704/1: format IOP Kconfig with tabs, create more consistency
[ARM] 3703/1: Add help description for ARCH_EP80219
[ARM] 3678/1: MMC: Make OMAP MMC work
[ARM] 3677/1: OMAP: Update H2 defconfig
[ARM] 3676/1: ARM: OMAP: Fix dmtimers and timer32k to compile on OMAP1
[ARM] Add section support to ioremap
[ARM] Fix sa11x0 SDRAM selection
[ARM] Set bit 4 on section mappings correctly depending on CPU
[ARM] 3666/1: TRIZEPS4 [1/5] core
ARM: OMAP: Multiplexing for 24xx GPMC wait pin monitoring
ARM: OMAP: Fix SRAM to use MT_MEMORY instead of MT_DEVICE
ARM: OMAP: Update dmtimers
ARM: OMAP: Make clock variables static
ARM: OMAP: Fix GPMC compilation when DEBUG is defined
ARM: OMAP: Mux updates for external DMA and GPIO
...
Diffstat (limited to 'arch/arm/kernel/iwmmxt-notifier.c')
-rw-r--r-- | arch/arm/kernel/iwmmxt-notifier.c | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/arch/arm/kernel/iwmmxt-notifier.c b/arch/arm/kernel/iwmmxt-notifier.c new file mode 100644 index 000000000000..44a86c33796e --- /dev/null +++ b/arch/arm/kernel/iwmmxt-notifier.c | |||
@@ -0,0 +1,64 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/kernel/iwmmxt-notifier.c | ||
3 | * | ||
4 | * XScale iWMMXt (Concan) context switching and handling | ||
5 | * | ||
6 | * Initial code: | ||
7 | * Copyright (c) 2003, Intel Corporation | ||
8 | * | ||
9 | * Full lazy switching support, optimizations and more, by Nicolas Pitre | ||
10 | * Copyright (c) 2003-2004, MontaVista Software, Inc. | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or modify | ||
13 | * it under the terms of the GNU General Public License version 2 as | ||
14 | * published by the Free Software Foundation. | ||
15 | */ | ||
16 | |||
17 | #include <linux/module.h> | ||
18 | #include <linux/config.h> | ||
19 | #include <linux/types.h> | ||
20 | #include <linux/kernel.h> | ||
21 | #include <linux/signal.h> | ||
22 | #include <linux/sched.h> | ||
23 | #include <linux/init.h> | ||
24 | #include <asm/thread_notify.h> | ||
25 | #include <asm/io.h> | ||
26 | |||
27 | static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t) | ||
28 | { | ||
29 | struct thread_info *thread = t; | ||
30 | |||
31 | switch (cmd) { | ||
32 | case THREAD_NOTIFY_FLUSH: | ||
33 | /* | ||
34 | * flush_thread() zeroes thread->fpstate, so no need | ||
35 | * to do anything here. | ||
36 | * | ||
37 | * FALLTHROUGH: Ensure we don't try to overwrite our newly | ||
38 | * initialised state information on the first fault. | ||
39 | */ | ||
40 | |||
41 | case THREAD_NOTIFY_RELEASE: | ||
42 | iwmmxt_task_release(thread); | ||
43 | break; | ||
44 | |||
45 | case THREAD_NOTIFY_SWITCH: | ||
46 | iwmmxt_task_switch(thread); | ||
47 | break; | ||
48 | } | ||
49 | |||
50 | return NOTIFY_DONE; | ||
51 | } | ||
52 | |||
53 | static struct notifier_block iwmmxt_notifier_block = { | ||
54 | .notifier_call = iwmmxt_do, | ||
55 | }; | ||
56 | |||
57 | static int __init iwmmxt_init(void) | ||
58 | { | ||
59 | thread_register_notifier(&iwmmxt_notifier_block); | ||
60 | |||
61 | return 0; | ||
62 | } | ||
63 | |||
64 | late_initcall(iwmmxt_init); | ||