[ARM] Set bit 4 on section mappings correctly depending on CPU

On some CPUs, bit 4 of section mappings means "update the
cache when written to".  On others, this bit is required to
be one, and others it's required to be zero.  Finally, on
ARMv6 and above, setting it turns on "no execute" and prevents
speculative prefetches.

With all these combinations, no one value fits all CPUs, so we
have to pick a value depending on the CPU type, and the area
we're mapping.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 2 insertions, 3 deletions

diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 330b9476c398..81cb902c487c 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -221,7 +221,7 @@ __create_page_tables:
         teq     r0, r6
         bne     1b
 
-        ldr     r7, [r10, #PROCINFO_MMUFLAGS]   @ mmuflags
+        ldr     r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
 
         /*
          * Create identity mapping for first MB of kernel to
@@ -272,8 +272,7 @@ __create_page_tables:
 #endif
 
 #ifdef CONFIG_DEBUG_LL
-        bic     r7, r7, #0x0c                   @ turn off cacheable
-                                                @ and bufferable bits
+        ldr     r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
         /*
          * Map in IO space for serial debugging.
          * This allows debug messages to be output