ARM: 6938/1: fiq: Refactor {get,set}_fiq_regs() for Thumb-2

 * To remove the risk of inconvenient register allocation decisions
   by the compiler, these functions are separated out as pure
   assembler.

 * The apcs frame manipulation code is not applicable for Thumb-2
   (and also not easily compatible).  Since it's not essential to
   have a full frame on these leaf assembler functions, the frame
   manipulation is removed, in the interests of simplicity.

 * Split up ldm/stm instructions to be compatible with Thumb-2,
   as well as avoiding instruction forms deprecated on >= ARMv7.

Signed-off-by: Dave Martin <dave.martin@linaro.org>
Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 49 insertions, 0 deletions

diff --git a/arch/arm/kernel/fiqasm.S b/arch/arm/kernel/fiqasm.S
new file mode 100644
index 000000000000..207f9d652010
--- /dev/null
+++ b/arch/arm/kernel/fiqasm.S
@@ -0,0 +1,49 @@
+/*
+ *  linux/arch/arm/kernel/fiqasm.S
+ *
+ *  Derived from code originally in linux/arch/arm/kernel/fiq.c:
+ *
+ *  Copyright (C) 1998 Russell King
+ *  Copyright (C) 1998, 1999 Phil Blundell
+ *  Copyright (C) 2011, Linaro Limited
+ *
+ *  FIQ support written by Philip Blundell <philb@gnu.org>, 1998.
+ *
+ *  FIQ support re-written by Russell King to be more generic
+ *
+ *  v7/Thumb-2 compatibility modifications by Linaro Limited, 2011.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+/*
+ * Taking an interrupt in FIQ mode is death, so both these functions
+ * disable irqs for the duration.
+ */
+
+ENTRY(__set_fiq_regs)
+        mov     r2, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
+        mrs     r1, cpsr
+        msr     cpsr_c, r2      @ select FIQ mode
+        mov     r0, r0          @ avoid hazard prior to ARMv4
+        ldmia   r0!, {r8 - r12}
+        ldr     sp, [r0], #4
+        ldr     lr, [r0]
+        msr     cpsr_c, r1      @ return to SVC mode
+        mov     r0, r0          @ avoid hazard prior to ARMv4
+        mov     pc, lr
+ENDPROC(__set_fiq_regs)
+
+ENTRY(__get_fiq_regs)
+        mov     r2, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
+        mrs     r1, cpsr
+        msr     cpsr_c, r2      @ select FIQ mode
+        mov     r0, r0          @ avoid hazard prior to ARMv4
+        stmia   r0!, {r8 - r12}
+        str     sp, [r0], #4
+        str     lr, [r0]
+        msr     cpsr_c, r1      @ return to SVC mode
+        mov     r0, r0          @ avoid hazard prior to ARMv4
+        mov     pc, lr
+ENDPROC(__get_fiq_regs)