diff options
author | Will Deacon <will.deacon@arm.com> | 2010-09-13 11:18:30 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-10-04 15:57:09 -0400 |
commit | 8925ec4c530094b878e7e28a1fd78e7122afd973 (patch) | |
tree | 2b7200f64892299c185d3a07d1f793ea9217b5d4 /arch/arm/include | |
parent | f8b63c184ad13cc8adc3dadb557d4fbc29f76e4d (diff) |
ARM: 6385/1: setup: detect aliasing I-cache when D-cache is non-aliasing
Currently, the Kernel assumes that if a CPU has a non-aliasing D-cache
then the I-cache is also non-aliasing. This may not be true on ARM cores
from v6 onwards, which may have aliasing I-caches but non-aliasing
D-caches.
This patch adds a cpu_has_aliasing_icache function, which is called from
cacheid_init and adds CACHEID_VIPT_I_ALIASING to the cacheid when
appropriate. A utility macro, icache_is_vipt_aliasing(), is also
provided.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/include')
-rw-r--r-- | arch/arm/include/asm/cachetype.h | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/include/asm/cachetype.h b/arch/arm/include/asm/cachetype.h index d3a4c2cb9f2f..c023db09fcc1 100644 --- a/arch/arm/include/asm/cachetype.h +++ b/arch/arm/include/asm/cachetype.h | |||
@@ -6,6 +6,7 @@ | |||
6 | #define CACHEID_VIPT_ALIASING (1 << 2) | 6 | #define CACHEID_VIPT_ALIASING (1 << 2) |
7 | #define CACHEID_VIPT (CACHEID_VIPT_ALIASING|CACHEID_VIPT_NONALIASING) | 7 | #define CACHEID_VIPT (CACHEID_VIPT_ALIASING|CACHEID_VIPT_NONALIASING) |
8 | #define CACHEID_ASID_TAGGED (1 << 3) | 8 | #define CACHEID_ASID_TAGGED (1 << 3) |
9 | #define CACHEID_VIPT_I_ALIASING (1 << 4) | ||
9 | 10 | ||
10 | extern unsigned int cacheid; | 11 | extern unsigned int cacheid; |
11 | 12 | ||
@@ -14,15 +15,18 @@ extern unsigned int cacheid; | |||
14 | #define cache_is_vipt_nonaliasing() cacheid_is(CACHEID_VIPT_NONALIASING) | 15 | #define cache_is_vipt_nonaliasing() cacheid_is(CACHEID_VIPT_NONALIASING) |
15 | #define cache_is_vipt_aliasing() cacheid_is(CACHEID_VIPT_ALIASING) | 16 | #define cache_is_vipt_aliasing() cacheid_is(CACHEID_VIPT_ALIASING) |
16 | #define icache_is_vivt_asid_tagged() cacheid_is(CACHEID_ASID_TAGGED) | 17 | #define icache_is_vivt_asid_tagged() cacheid_is(CACHEID_ASID_TAGGED) |
18 | #define icache_is_vipt_aliasing() cacheid_is(CACHEID_VIPT_I_ALIASING) | ||
17 | 19 | ||
18 | /* | 20 | /* |
19 | * __LINUX_ARM_ARCH__ is the minimum supported CPU architecture | 21 | * __LINUX_ARM_ARCH__ is the minimum supported CPU architecture |
20 | * Mask out support which will never be present on newer CPUs. | 22 | * Mask out support which will never be present on newer CPUs. |
21 | * - v6+ is never VIVT | 23 | * - v6+ is never VIVT |
22 | * - v7+ VIPT never aliases | 24 | * - v7+ VIPT never aliases on D-side |
23 | */ | 25 | */ |
24 | #if __LINUX_ARM_ARCH__ >= 7 | 26 | #if __LINUX_ARM_ARCH__ >= 7 |
25 | #define __CACHEID_ARCH_MIN (CACHEID_VIPT_NONALIASING | CACHEID_ASID_TAGGED) | 27 | #define __CACHEID_ARCH_MIN (CACHEID_VIPT_NONALIASING |\ |
28 | CACHEID_ASID_TAGGED |\ | ||
29 | CACHEID_VIPT_I_ALIASING) | ||
26 | #elif __LINUX_ARM_ARCH__ >= 6 | 30 | #elif __LINUX_ARM_ARCH__ >= 6 |
27 | #define __CACHEID_ARCH_MIN (~CACHEID_VIVT) | 31 | #define __CACHEID_ARCH_MIN (~CACHEID_VIVT) |
28 | #else | 32 | #else |