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authorAnders Larsen <al@alarsen.net>2010-04-08 06:48:16 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-04-09 03:31:04 -0400
commit9823f1a8463fb631fe965110fe19adeb3df239c4 (patch)
treee55e3f1a8ba2f1dee33a3d189061027e34fd4c15 /arch/arm/include
parentbb3c9d4f851d51bb6302ef0df830dcec88d7c529 (diff)
ARM: 6043/1: AT91 slow-clock resume: Don't wait for a disabled PLL to lock
at91 slow-clock resume: Don't wait for a disabled PLL to lock. We run into this problem with the PLLB on the at91: ohci-at91 disables the PLLB when going to suspend. The slowclock code however tries to do the same: It saves the PLLB register value and when restoring the value during resume, it waits for the PLLB to lock again. However the PLL will never lock and the loop would run into its timeout because the slowclock code just stored and restored an empty register. This fixes the problem by only restoring PLLA/PLLB when they were enabled at suspend time. Cc: Andrew Victor <avictor.za@gmail.com> Signed-off-by: Anders Larsen <al@alarsen.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/include')
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