Merge branch 'for-rmk' of git://linux-arm.org/linux-2.6 into devel

Conflicts:
	arch/arm/Kconfig
	arch/arm/kernel/smp.c
	arch/arm/mach-realview/Makefile
	arch/arm/mach-realview/platsmp.c

5 files changed, 69 insertions, 2 deletions

diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index 7b9d27e749b8..b3e656c6fb78 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -8,6 +8,21 @@
 #define CPUID_TCM       2
 #define CPUID_TLBTYPE   3
 
+#define CPUID_EXT_PFR0  "c1, 0"
+#define CPUID_EXT_PFR1  "c1, 1"
+#define CPUID_EXT_DFR0  "c1, 2"
+#define CPUID_EXT_AFR0  "c1, 3"
+#define CPUID_EXT_MMFR0 "c1, 4"
+#define CPUID_EXT_MMFR1 "c1, 5"
+#define CPUID_EXT_MMFR2 "c1, 6"
+#define CPUID_EXT_MMFR3 "c1, 7"
+#define CPUID_EXT_ISAR0 "c2, 0"
+#define CPUID_EXT_ISAR1 "c2, 1"
+#define CPUID_EXT_ISAR2 "c2, 2"
+#define CPUID_EXT_ISAR3 "c2, 3"
+#define CPUID_EXT_ISAR4 "c2, 4"
+#define CPUID_EXT_ISAR5 "c2, 5"
+
 #ifdef CONFIG_CPU_CP15
 #define read_cpuid(reg)                                                 \
         ({                                                              \
@@ -18,9 +33,19 @@
                     : "cc");                                            \
                 __val;                                                  \
         })
+#define read_cpuid_ext(ext_reg)                                         \
+        ({                                                              \
+                unsigned int __val;                                     \
+                asm("mrc        p15, 0, %0, c0, " ext_reg               \
+                    : "=r" (__val)                                      \
+                    :                                                   \
+                    : "cc");                                            \
+                __val;                                                  \
+        })
 #else
 extern unsigned int processor_id;
 #define read_cpuid(reg) (processor_id)
+#define read_cpuid_ext(reg) 0
 #endif
 
 /*
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 64f2252a25cd..cdb9022716fd 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -24,6 +24,8 @@
 #define L2X0_CACHE_TYPE                 0x004
 #define L2X0_CTRL                       0x100
 #define L2X0_AUX_CTRL                   0x104
+#define L2X0_TAG_LATENCY_CTRL           0x108
+#define L2X0_DATA_LATENCY_CTRL          0x10C
 #define L2X0_EVENT_CNT_CTRL             0x200
 #define L2X0_EVENT_CNT1_CFG             0x204
 #define L2X0_EVENT_CNT0_CFG             0x208
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index 1845892260e7..6a89567ffc5b 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -71,6 +71,7 @@ struct thread_struct {
                 regs->ARM_cpsr = USR26_MODE;                            \
         if (elf_hwcap & HWCAP_THUMB && pc & 1)                          \
                 regs->ARM_cpsr |= PSR_T_BIT;                            \
+        regs->ARM_cpsr |= PSR_ENDSTATE;                                 \
         regs->ARM_pc = pc & ~1;         /* pc */                        \
         regs->ARM_sp = sp;              /* sp */                        \
         regs->ARM_r2 = stack[2];        /* r2 (envp) */                 \
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 236a06b9b7ce..67b833c9b6b9 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -50,6 +50,7 @@
 #define PSR_F_BIT       0x00000040
 #define PSR_I_BIT       0x00000080
 #define PSR_A_BIT       0x00000100
+#define PSR_E_BIT       0x00000200
 #define PSR_J_BIT       0x01000000
 #define PSR_Q_BIT       0x08000000
 #define PSR_V_BIT       0x10000000
@@ -65,6 +66,22 @@
 #define PSR_x           0x0000ff00      /* Extension            */
 #define PSR_c           0x000000ff      /* Control              */
 
+/*
+ * ARMv7 groups of APSR bits
+ */
+#define PSR_ISET_MASK   0x01000010      /* ISA state (J, T) mask */
+#define PSR_IT_MASK     0x0600fc00      /* If-Then execution state mask */
+#define PSR_ENDIAN_MASK 0x00000200      /* Endianness state mask */
+
+/*
+ * Default endianness state
+ */
+#ifdef CONFIG_CPU_ENDIAN_BE8
+#define PSR_ENDSTATE    PSR_E_BIT
+#else
+#define PSR_ENDSTATE    0
+#endif
+
 #ifndef __ASSEMBLY__
 
 /*
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index a62218013c78..c964f3fc3bc5 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -40,6 +40,12 @@
 #define TLB_V6_I_ASID   (1 << 18)
 
 #define TLB_BTB         (1 << 28)
+
+/* Unified Inner Shareable TLB operations (ARMv7 MP extensions) */
+#define TLB_V7_UIS_PAGE (1 << 19)
+#define TLB_V7_UIS_FULL (1 << 20)
+#define TLB_V7_UIS_ASID (1 << 21)
+
 #define TLB_L2CLEAN_FR  (1 << 29)               /* Feroceon */
 #define TLB_DCLEAN      (1 << 30)
 #define TLB_WB          (1 << 31)
@@ -176,9 +182,17 @@
 # define v6wbi_always_flags     (-1UL)
 #endif
 
+#ifdef CONFIG_SMP
+#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
+                         TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
+#else
+#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
+                         TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID)
+#endif
+
 #ifdef CONFIG_CPU_TLB_V7
-# define v7wbi_possible_flags   v6wbi_tlb_flags
-# define v7wbi_always_flags     v6wbi_tlb_flags
+# define v7wbi_possible_flags   v7wbi_tlb_flags
+# define v7wbi_always_flags     v7wbi_tlb_flags
 # ifdef _TLB
 #  define MULTI_TLB 1
 # else
@@ -316,6 +330,8 @@ static inline void local_flush_tlb_all(void)
                 asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
         if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL))
                 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
+        if (tlb_flag(TLB_V7_UIS_FULL))
+                asm("mcr p15, 0, %0, c8, c3, 0" : : "r" (zero) : "cc");
 
         if (tlb_flag(TLB_BTB)) {
                 /* flush the branch target cache */
@@ -351,6 +367,8 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
                 asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc");
         if (tlb_flag(TLB_V6_I_ASID))
                 asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc");
+        if (tlb_flag(TLB_V7_UIS_ASID))
+                asm("mcr p15, 0, %0, c8, c3, 2" : : "r" (asid) : "cc");
 
         if (tlb_flag(TLB_BTB)) {
                 /* flush the branch target cache */
@@ -389,6 +407,8 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
                 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
         if (tlb_flag(TLB_V6_I_PAGE))
                 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
+        if (tlb_flag(TLB_V7_UIS_PAGE))
+                asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (uaddr) : "cc");
 
         if (tlb_flag(TLB_BTB)) {
                 /* flush the branch target cache */
@@ -424,6 +444,8 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
                 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
         if (tlb_flag(TLB_V6_I_PAGE))
                 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
+        if (tlb_flag(TLB_V7_UIS_PAGE))
+                asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (kaddr) : "cc");
 
         if (tlb_flag(TLB_BTB)) {
                 /* flush the branch target cache */