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authorLinus Torvalds <torvalds@linux-foundation.org>2013-07-02 16:43:38 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-07-02 16:43:38 -0400
commit3883cbb6c1bda013a3ce2dbdab7dc97c52e4a232 (patch)
tree5b69f83b049d24ac81123ac954ca8c9128e48443 /arch/arm/include
parentd2033f2c1d1de2239ded15e478ddb4028f192a15 (diff)
parent1eb92b24e243085d242cf5ffd64829bba70972e1 (diff)
Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC specific changes from Arnd Bergmann: "These changes are all to SoC-specific code, a total of 33 branches on 17 platforms were pulled into this. Like last time, Renesas sh-mobile is now the platform with the most changes, followed by OMAP and EXYNOS. Two new platforms, TI Keystone and Rockchips RK3xxx are added in this branch, both containing almost no platform specific code at all, since they are using generic subsystem interfaces for clocks, pinctrl, interrupts etc. The device drivers are getting merged through the respective subsystem maintainer trees. One more SoC (u300) is now multiplatform capable and several others (shmobile, exynos, msm, integrator, kirkwood, clps711x) are moving towards that goal with this series but need more work. Also noteworthy is the work on PCI here, which is traditionally part of the SoC specific code. With the changes done by Thomas Petazzoni, we can now more easily have PCI host controller drivers as loadable modules and keep them separate from the platform code in drivers/pci/host. This has already led to the discovery that three platforms (exynos, spear and imx) are actually using an identical PCIe host controller and will be able to share a driver once support for spear and imx is added." * tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (480 commits) ARM: integrator: let pciv3 use mem/premem from device tree ARM: integrator: set local side PCI addresses right ARM: dts: Add pcie controller node for exynos5440-ssdk5440 ARM: dts: Add pcie controller node for Samsung EXYNOS5440 SoC ARM: EXYNOS: Enable PCIe support for Exynos5440 pci: Add PCIe driver for Samsung Exynos ARM: OMAP5: voltagedomain data: remove temporary OMAP4 voltage data ARM: keystone: Move CPU bringup code to dedicated asm file ARM: multiplatform: always pick one CPU type ARM: imx: select syscon for IMX6SL ARM: keystone: select ARM_ERRATA_798181 only for SMP ARM: imx: Synertronixx scb9328 needs to select SOC_IMX1 ARM: OMAP2+: AM43x: resolve SMP related build error dmaengine: edma: enable build for AM33XX ARM: edma: Add EDMA crossbar event mux support ARM: edma: Add DT and runtime PM support to the private EDMA API dmaengine: edma: Add TI EDMA device tree binding arm: add basic support for Rockchip RK3066a boards arm: add debug uarts for rockchip rk29xx and rk3xxx series arm: Add basic clocks for Rockchip rk3066a SoCs ...
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/assembler.h17
-rw-r--r--arch/arm/include/asm/cp15.h14
-rw-r--r--arch/arm/include/asm/cputype.h44
-rw-r--r--arch/arm/include/asm/glue-cache.h27
-rw-r--r--arch/arm/include/asm/glue-df.h8
-rw-r--r--arch/arm/include/asm/glue-proc.h9
-rw-r--r--arch/arm/include/asm/hardware/pci_v3.h186
-rw-r--r--arch/arm/include/asm/irqflags.h22
-rw-r--r--arch/arm/include/asm/mach/arch.h5
-rw-r--r--arch/arm/include/asm/mach/pci.h17
-rw-r--r--arch/arm/include/asm/psci.h9
-rw-r--r--arch/arm/include/asm/ptrace.h4
-rw-r--r--arch/arm/include/asm/system_info.h1
-rw-r--r--arch/arm/include/asm/v7m.h44
-rw-r--r--arch/arm/include/debug/imx-uart.h10
-rw-r--r--arch/arm/include/debug/keystone.S43
-rw-r--r--arch/arm/include/debug/mvebu.S5
-rw-r--r--arch/arm/include/debug/rockchip.S42
-rw-r--r--arch/arm/include/debug/u300.S18
-rw-r--r--arch/arm/include/uapi/asm/ptrace.h35
20 files changed, 351 insertions, 209 deletions
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 05ee9eebad6b..a5fef710af32 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -136,7 +136,11 @@
136 * assumes FIQs are enabled, and that the processor is in SVC mode. 136 * assumes FIQs are enabled, and that the processor is in SVC mode.
137 */ 137 */
138 .macro save_and_disable_irqs, oldcpsr 138 .macro save_and_disable_irqs, oldcpsr
139#ifdef CONFIG_CPU_V7M
140 mrs \oldcpsr, primask
141#else
139 mrs \oldcpsr, cpsr 142 mrs \oldcpsr, cpsr
143#endif
140 disable_irq 144 disable_irq
141 .endm 145 .endm
142 146
@@ -150,7 +154,11 @@
150 * guarantee that this will preserve the flags. 154 * guarantee that this will preserve the flags.
151 */ 155 */
152 .macro restore_irqs_notrace, oldcpsr 156 .macro restore_irqs_notrace, oldcpsr
157#ifdef CONFIG_CPU_V7M
158 msr primask, \oldcpsr
159#else
153 msr cpsr_c, \oldcpsr 160 msr cpsr_c, \oldcpsr
161#endif
154 .endm 162 .endm
155 163
156 .macro restore_irqs, oldcpsr 164 .macro restore_irqs, oldcpsr
@@ -229,7 +237,14 @@
229#endif 237#endif
230 .endm 238 .endm
231 239
232#ifdef CONFIG_THUMB2_KERNEL 240#if defined(CONFIG_CPU_V7M)
241 /*
242 * setmode is used to assert to be in svc mode during boot. For v7-M
243 * this is done in __v7m_setup, so setmode can be empty here.
244 */
245 .macro setmode, mode, reg
246 .endm
247#elif defined(CONFIG_THUMB2_KERNEL)
233 .macro setmode, mode, reg 248 .macro setmode, mode, reg
234 mov \reg, #\mode 249 mov \reg, #\mode
235 msr cpsr_c, \reg 250 msr cpsr_c, \reg
diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h
index 1f3262e99d81..cedd3721318b 100644
--- a/arch/arm/include/asm/cp15.h
+++ b/arch/arm/include/asm/cp15.h
@@ -61,6 +61,20 @@ static inline void set_cr(unsigned int val)
61 isb(); 61 isb();
62} 62}
63 63
64static inline unsigned int get_auxcr(void)
65{
66 unsigned int val;
67 asm("mrc p15, 0, %0, c1, c0, 1 @ get AUXCR" : "=r" (val));
68 return val;
69}
70
71static inline void set_auxcr(unsigned int val)
72{
73 asm volatile("mcr p15, 0, %0, c1, c0, 1 @ set AUXCR"
74 : : "r" (val));
75 isb();
76}
77
64#ifndef CONFIG_SMP 78#ifndef CONFIG_SMP
65extern void adjust_cr(unsigned long mask, unsigned long set); 79extern void adjust_cr(unsigned long mask, unsigned long set);
66#endif 80#endif
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index dba62cb1ad08..d7deb62554c9 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -10,6 +10,22 @@
10#define CPUID_TLBTYPE 3 10#define CPUID_TLBTYPE 3
11#define CPUID_MPIDR 5 11#define CPUID_MPIDR 5
12 12
13#ifdef CONFIG_CPU_V7M
14#define CPUID_EXT_PFR0 0x40
15#define CPUID_EXT_PFR1 0x44
16#define CPUID_EXT_DFR0 0x48
17#define CPUID_EXT_AFR0 0x4c
18#define CPUID_EXT_MMFR0 0x50
19#define CPUID_EXT_MMFR1 0x54
20#define CPUID_EXT_MMFR2 0x58
21#define CPUID_EXT_MMFR3 0x5c
22#define CPUID_EXT_ISAR0 0x60
23#define CPUID_EXT_ISAR1 0x64
24#define CPUID_EXT_ISAR2 0x68
25#define CPUID_EXT_ISAR3 0x6c
26#define CPUID_EXT_ISAR4 0x70
27#define CPUID_EXT_ISAR5 0x74
28#else
13#define CPUID_EXT_PFR0 "c1, 0" 29#define CPUID_EXT_PFR0 "c1, 0"
14#define CPUID_EXT_PFR1 "c1, 1" 30#define CPUID_EXT_PFR1 "c1, 1"
15#define CPUID_EXT_DFR0 "c1, 2" 31#define CPUID_EXT_DFR0 "c1, 2"
@@ -24,6 +40,7 @@
24#define CPUID_EXT_ISAR3 "c2, 3" 40#define CPUID_EXT_ISAR3 "c2, 3"
25#define CPUID_EXT_ISAR4 "c2, 4" 41#define CPUID_EXT_ISAR4 "c2, 4"
26#define CPUID_EXT_ISAR5 "c2, 5" 42#define CPUID_EXT_ISAR5 "c2, 5"
43#endif
27 44
28#define MPIDR_SMP_BITMASK (0x3 << 30) 45#define MPIDR_SMP_BITMASK (0x3 << 30)
29#define MPIDR_SMP_VALUE (0x2 << 30) 46#define MPIDR_SMP_VALUE (0x2 << 30)
@@ -81,7 +98,23 @@ extern unsigned int processor_id;
81 __val; \ 98 __val; \
82 }) 99 })
83 100
84#else /* ifdef CONFIG_CPU_CP15 */ 101#elif defined(CONFIG_CPU_V7M)
102
103#include <asm/io.h>
104#include <asm/v7m.h>
105
106#define read_cpuid(reg) \
107 ({ \
108 WARN_ON_ONCE(1); \
109 0; \
110 })
111
112static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)
113{
114 return readl(BASEADDR_V7M_SCB + offset);
115}
116
117#else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */
85 118
86/* 119/*
87 * read_cpuid and read_cpuid_ext should only ever be called on machines that 120 * read_cpuid and read_cpuid_ext should only ever be called on machines that
@@ -108,7 +141,14 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void)
108 return read_cpuid(CPUID_ID); 141 return read_cpuid(CPUID_ID);
109} 142}
110 143
111#else /* ifdef CONFIG_CPU_CP15 */ 144#elif defined(CONFIG_CPU_V7M)
145
146static inline unsigned int __attribute_const__ read_cpuid_id(void)
147{
148 return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
149}
150
151#else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */
112 152
113static inline unsigned int __attribute_const__ read_cpuid_id(void) 153static inline unsigned int __attribute_const__ read_cpuid_id(void)
114{ 154{
diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h
index ea289e1435e7..c81adc08b3fb 100644
--- a/arch/arm/include/asm/glue-cache.h
+++ b/arch/arm/include/asm/glue-cache.h
@@ -117,10 +117,37 @@
117# endif 117# endif
118#endif 118#endif
119 119
120#if defined(CONFIG_CPU_V7M)
121# ifdef _CACHE
122# define MULTI_CACHE 1
123# else
124# define _CACHE nop
125# endif
126#endif
127
120#if !defined(_CACHE) && !defined(MULTI_CACHE) 128#if !defined(_CACHE) && !defined(MULTI_CACHE)
121#error Unknown cache maintenance model 129#error Unknown cache maintenance model
122#endif 130#endif
123 131
132#ifndef __ASSEMBLER__
133extern inline void nop_flush_icache_all(void) { }
134extern inline void nop_flush_kern_cache_all(void) { }
135extern inline void nop_flush_kern_cache_louis(void) { }
136extern inline void nop_flush_user_cache_all(void) { }
137extern inline void nop_flush_user_cache_range(unsigned long a,
138 unsigned long b, unsigned int c) { }
139
140extern inline void nop_coherent_kern_range(unsigned long a, unsigned long b) { }
141extern inline int nop_coherent_user_range(unsigned long a,
142 unsigned long b) { return 0; }
143extern inline void nop_flush_kern_dcache_area(void *a, size_t s) { }
144
145extern inline void nop_dma_flush_range(const void *a, const void *b) { }
146
147extern inline void nop_dma_map_area(const void *s, size_t l, int f) { }
148extern inline void nop_dma_unmap_area(const void *s, size_t l, int f) { }
149#endif
150
124#ifndef MULTI_CACHE 151#ifndef MULTI_CACHE
125#define __cpuc_flush_icache_all __glue(_CACHE,_flush_icache_all) 152#define __cpuc_flush_icache_all __glue(_CACHE,_flush_icache_all)
126#define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all) 153#define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all)
diff --git a/arch/arm/include/asm/glue-df.h b/arch/arm/include/asm/glue-df.h
index b6e9f2c108b5..6b70f1b46a6e 100644
--- a/arch/arm/include/asm/glue-df.h
+++ b/arch/arm/include/asm/glue-df.h
@@ -95,6 +95,14 @@
95# endif 95# endif
96#endif 96#endif
97 97
98#ifdef CONFIG_CPU_ABRT_NOMMU
99# ifdef CPU_DABORT_HANDLER
100# define MULTI_DABORT 1
101# else
102# define CPU_DABORT_HANDLER nommu_early_abort
103# endif
104#endif
105
98#ifndef CPU_DABORT_HANDLER 106#ifndef CPU_DABORT_HANDLER
99#error Unknown data abort handler type 107#error Unknown data abort handler type
100#endif 108#endif
diff --git a/arch/arm/include/asm/glue-proc.h b/arch/arm/include/asm/glue-proc.h
index 8017e94acc5e..e6168c0c18e9 100644
--- a/arch/arm/include/asm/glue-proc.h
+++ b/arch/arm/include/asm/glue-proc.h
@@ -239,6 +239,15 @@
239# endif 239# endif
240#endif 240#endif
241 241
242#ifdef CONFIG_CPU_V7M
243# ifdef CPU_NAME
244# undef MULTI_CPU
245# define MULTI_CPU
246# else
247# define CPU_NAME cpu_v7m
248# endif
249#endif
250
242#ifndef MULTI_CPU 251#ifndef MULTI_CPU
243#define cpu_proc_init __glue(CPU_NAME,_proc_init) 252#define cpu_proc_init __glue(CPU_NAME,_proc_init)
244#define cpu_proc_fin __glue(CPU_NAME,_proc_fin) 253#define cpu_proc_fin __glue(CPU_NAME,_proc_fin)
diff --git a/arch/arm/include/asm/hardware/pci_v3.h b/arch/arm/include/asm/hardware/pci_v3.h
deleted file mode 100644
index 2811c7e2cfdf..000000000000
--- a/arch/arm/include/asm/hardware/pci_v3.h
+++ /dev/null
@@ -1,186 +0,0 @@
1/*
2 * arch/arm/include/asm/hardware/pci_v3.h
3 *
4 * Internal header file PCI V3 chip
5 *
6 * Copyright (C) ARM Limited
7 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23#ifndef ASM_ARM_HARDWARE_PCI_V3_H
24#define ASM_ARM_HARDWARE_PCI_V3_H
25
26/* -------------------------------------------------------------------------------
27 * V3 Local Bus to PCI Bridge definitions
28 * -------------------------------------------------------------------------------
29 * Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04
30 * All V3 register names are prefaced by V3_ to avoid clashing with any other
31 * PCI definitions. Their names match the user's manual.
32 *
33 * I'm assuming that I20 is disabled.
34 *
35 */
36#define V3_PCI_VENDOR 0x00000000
37#define V3_PCI_DEVICE 0x00000002
38#define V3_PCI_CMD 0x00000004
39#define V3_PCI_STAT 0x00000006
40#define V3_PCI_CC_REV 0x00000008
41#define V3_PCI_HDR_CFG 0x0000000C
42#define V3_PCI_IO_BASE 0x00000010
43#define V3_PCI_BASE0 0x00000014
44#define V3_PCI_BASE1 0x00000018
45#define V3_PCI_SUB_VENDOR 0x0000002C
46#define V3_PCI_SUB_ID 0x0000002E
47#define V3_PCI_ROM 0x00000030
48#define V3_PCI_BPARAM 0x0000003C
49#define V3_PCI_MAP0 0x00000040
50#define V3_PCI_MAP1 0x00000044
51#define V3_PCI_INT_STAT 0x00000048
52#define V3_PCI_INT_CFG 0x0000004C
53#define V3_LB_BASE0 0x00000054
54#define V3_LB_BASE1 0x00000058
55#define V3_LB_MAP0 0x0000005E
56#define V3_LB_MAP1 0x00000062
57#define V3_LB_BASE2 0x00000064
58#define V3_LB_MAP2 0x00000066
59#define V3_LB_SIZE 0x00000068
60#define V3_LB_IO_BASE 0x0000006E
61#define V3_FIFO_CFG 0x00000070
62#define V3_FIFO_PRIORITY 0x00000072
63#define V3_FIFO_STAT 0x00000074
64#define V3_LB_ISTAT 0x00000076
65#define V3_LB_IMASK 0x00000077
66#define V3_SYSTEM 0x00000078
67#define V3_LB_CFG 0x0000007A
68#define V3_PCI_CFG 0x0000007C
69#define V3_DMA_PCI_ADR0 0x00000080
70#define V3_DMA_PCI_ADR1 0x00000090
71#define V3_DMA_LOCAL_ADR0 0x00000084
72#define V3_DMA_LOCAL_ADR1 0x00000094
73#define V3_DMA_LENGTH0 0x00000088
74#define V3_DMA_LENGTH1 0x00000098
75#define V3_DMA_CSR0 0x0000008B
76#define V3_DMA_CSR1 0x0000009B
77#define V3_DMA_CTLB_ADR0 0x0000008C
78#define V3_DMA_CTLB_ADR1 0x0000009C
79#define V3_DMA_DELAY 0x000000E0
80#define V3_MAIL_DATA 0x000000C0
81#define V3_PCI_MAIL_IEWR 0x000000D0
82#define V3_PCI_MAIL_IERD 0x000000D2
83#define V3_LB_MAIL_IEWR 0x000000D4
84#define V3_LB_MAIL_IERD 0x000000D6
85#define V3_MAIL_WR_STAT 0x000000D8
86#define V3_MAIL_RD_STAT 0x000000DA
87#define V3_QBA_MAP 0x000000DC
88
89/* PCI COMMAND REGISTER bits
90 */
91#define V3_COMMAND_M_FBB_EN (1 << 9)
92#define V3_COMMAND_M_SERR_EN (1 << 8)
93#define V3_COMMAND_M_PAR_EN (1 << 6)
94#define V3_COMMAND_M_MASTER_EN (1 << 2)
95#define V3_COMMAND_M_MEM_EN (1 << 1)
96#define V3_COMMAND_M_IO_EN (1 << 0)
97
98/* SYSTEM REGISTER bits
99 */
100#define V3_SYSTEM_M_RST_OUT (1 << 15)
101#define V3_SYSTEM_M_LOCK (1 << 14)
102
103/* PCI_CFG bits
104 */
105#define V3_PCI_CFG_M_I2O_EN (1 << 15)
106#define V3_PCI_CFG_M_IO_REG_DIS (1 << 14)
107#define V3_PCI_CFG_M_IO_DIS (1 << 13)
108#define V3_PCI_CFG_M_EN3V (1 << 12)
109#define V3_PCI_CFG_M_RETRY_EN (1 << 10)
110#define V3_PCI_CFG_M_AD_LOW1 (1 << 9)
111#define V3_PCI_CFG_M_AD_LOW0 (1 << 8)
112
113/* PCI_BASE register bits (PCI -> Local Bus)
114 */
115#define V3_PCI_BASE_M_ADR_BASE 0xFFF00000
116#define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00
117#define V3_PCI_BASE_M_PREFETCH (1 << 3)
118#define V3_PCI_BASE_M_TYPE (3 << 1)
119#define V3_PCI_BASE_M_IO (1 << 0)
120
121/* PCI MAP register bits (PCI -> Local bus)
122 */
123#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000
124#define V3_PCI_MAP_M_RD_POST_INH (1 << 15)
125#define V3_PCI_MAP_M_ROM_SIZE (3 << 10)
126#define V3_PCI_MAP_M_SWAP (3 << 8)
127#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0
128#define V3_PCI_MAP_M_REG_EN (1 << 1)
129#define V3_PCI_MAP_M_ENABLE (1 << 0)
130
131/*
132 * LB_BASE0,1 register bits (Local bus -> PCI)
133 */
134#define V3_LB_BASE_ADR_BASE 0xfff00000
135#define V3_LB_BASE_SWAP (3 << 8)
136#define V3_LB_BASE_ADR_SIZE (15 << 4)
137#define V3_LB_BASE_PREFETCH (1 << 3)
138#define V3_LB_BASE_ENABLE (1 << 0)
139
140#define V3_LB_BASE_ADR_SIZE_1MB (0 << 4)
141#define V3_LB_BASE_ADR_SIZE_2MB (1 << 4)
142#define V3_LB_BASE_ADR_SIZE_4MB (2 << 4)
143#define V3_LB_BASE_ADR_SIZE_8MB (3 << 4)
144#define V3_LB_BASE_ADR_SIZE_16MB (4 << 4)
145#define V3_LB_BASE_ADR_SIZE_32MB (5 << 4)
146#define V3_LB_BASE_ADR_SIZE_64MB (6 << 4)
147#define V3_LB_BASE_ADR_SIZE_128MB (7 << 4)
148#define V3_LB_BASE_ADR_SIZE_256MB (8 << 4)
149#define V3_LB_BASE_ADR_SIZE_512MB (9 << 4)
150#define V3_LB_BASE_ADR_SIZE_1GB (10 << 4)
151#define V3_LB_BASE_ADR_SIZE_2GB (11 << 4)
152
153#define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE)
154
155/*
156 * LB_MAP0,1 register bits (Local bus -> PCI)
157 */
158#define V3_LB_MAP_MAP_ADR 0xfff0
159#define V3_LB_MAP_TYPE (7 << 1)
160#define V3_LB_MAP_AD_LOW_EN (1 << 0)
161
162#define V3_LB_MAP_TYPE_IACK (0 << 1)
163#define V3_LB_MAP_TYPE_IO (1 << 1)
164#define V3_LB_MAP_TYPE_MEM (3 << 1)
165#define V3_LB_MAP_TYPE_CONFIG (5 << 1)
166#define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1)
167
168#define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR)
169
170/*
171 * LB_BASE2 register bits (Local bus -> PCI IO)
172 */
173#define V3_LB_BASE2_ADR_BASE 0xff00
174#define V3_LB_BASE2_SWAP (3 << 6)
175#define V3_LB_BASE2_ENABLE (1 << 0)
176
177#define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE)
178
179/*
180 * LB_MAP2 register bits (Local bus -> PCI IO)
181 */
182#define V3_LB_MAP2_MAP_ADR 0xff00
183
184#define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR)
185
186#endif
diff --git a/arch/arm/include/asm/irqflags.h b/arch/arm/include/asm/irqflags.h
index 1e6cca55c750..3b763d6652a0 100644
--- a/arch/arm/include/asm/irqflags.h
+++ b/arch/arm/include/asm/irqflags.h
@@ -8,6 +8,16 @@
8/* 8/*
9 * CPU interrupt mask handling. 9 * CPU interrupt mask handling.
10 */ 10 */
11#ifdef CONFIG_CPU_V7M
12#define IRQMASK_REG_NAME_R "primask"
13#define IRQMASK_REG_NAME_W "primask"
14#define IRQMASK_I_BIT 1
15#else
16#define IRQMASK_REG_NAME_R "cpsr"
17#define IRQMASK_REG_NAME_W "cpsr_c"
18#define IRQMASK_I_BIT PSR_I_BIT
19#endif
20
11#if __LINUX_ARM_ARCH__ >= 6 21#if __LINUX_ARM_ARCH__ >= 6
12 22
13static inline unsigned long arch_local_irq_save(void) 23static inline unsigned long arch_local_irq_save(void)
@@ -15,7 +25,7 @@ static inline unsigned long arch_local_irq_save(void)
15 unsigned long flags; 25 unsigned long flags;
16 26
17 asm volatile( 27 asm volatile(
18 " mrs %0, cpsr @ arch_local_irq_save\n" 28 " mrs %0, " IRQMASK_REG_NAME_R " @ arch_local_irq_save\n"
19 " cpsid i" 29 " cpsid i"
20 : "=r" (flags) : : "memory", "cc"); 30 : "=r" (flags) : : "memory", "cc");
21 return flags; 31 return flags;
@@ -129,7 +139,7 @@ static inline unsigned long arch_local_save_flags(void)
129{ 139{
130 unsigned long flags; 140 unsigned long flags;
131 asm volatile( 141 asm volatile(
132 " mrs %0, cpsr @ local_save_flags" 142 " mrs %0, " IRQMASK_REG_NAME_R " @ local_save_flags"
133 : "=r" (flags) : : "memory", "cc"); 143 : "=r" (flags) : : "memory", "cc");
134 return flags; 144 return flags;
135} 145}
@@ -140,7 +150,7 @@ static inline unsigned long arch_local_save_flags(void)
140static inline void arch_local_irq_restore(unsigned long flags) 150static inline void arch_local_irq_restore(unsigned long flags)
141{ 151{
142 asm volatile( 152 asm volatile(
143 " msr cpsr_c, %0 @ local_irq_restore" 153 " msr " IRQMASK_REG_NAME_W ", %0 @ local_irq_restore"
144 : 154 :
145 : "r" (flags) 155 : "r" (flags)
146 : "memory", "cc"); 156 : "memory", "cc");
@@ -148,8 +158,8 @@ static inline void arch_local_irq_restore(unsigned long flags)
148 158
149static inline int arch_irqs_disabled_flags(unsigned long flags) 159static inline int arch_irqs_disabled_flags(unsigned long flags)
150{ 160{
151 return flags & PSR_I_BIT; 161 return flags & IRQMASK_I_BIT;
152} 162}
153 163
154#endif 164#endif /* ifdef __KERNEL__ */
155#endif 165#endif /* ifndef __ASM_ARM_IRQFLAGS_H */
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 308ad7d6f98b..75bf07910b81 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -8,6 +8,8 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11#include <linux/types.h>
12
11#ifndef __ASSEMBLY__ 13#ifndef __ASSEMBLY__
12 14
13struct tag; 15struct tag;
@@ -16,8 +18,10 @@ struct pt_regs;
16struct smp_operations; 18struct smp_operations;
17#ifdef CONFIG_SMP 19#ifdef CONFIG_SMP
18#define smp_ops(ops) (&(ops)) 20#define smp_ops(ops) (&(ops))
21#define smp_init_ops(ops) (&(ops))
19#else 22#else
20#define smp_ops(ops) (struct smp_operations *)NULL 23#define smp_ops(ops) (struct smp_operations *)NULL
24#define smp_init_ops(ops) (bool (*)(void))NULL
21#endif 25#endif
22 26
23struct machine_desc { 27struct machine_desc {
@@ -41,6 +45,7 @@ struct machine_desc {
41 unsigned char reserve_lp2 :1; /* never has lp2 */ 45 unsigned char reserve_lp2 :1; /* never has lp2 */
42 char restart_mode; /* default restart mode */ 46 char restart_mode; /* default restart mode */
43 struct smp_operations *smp; /* SMP operations */ 47 struct smp_operations *smp; /* SMP operations */
48 bool (*smp_init)(void);
44 void (*fixup)(struct tag *, char **, 49 void (*fixup)(struct tag *, char **,
45 struct meminfo *); 50 struct meminfo *);
46 void (*reserve)(void);/* reserve mem blocks */ 51 void (*reserve)(void);/* reserve mem blocks */
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index 7d2c3c843801..a1c90d7feb0e 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -16,6 +16,7 @@
16struct pci_sys_data; 16struct pci_sys_data;
17struct pci_ops; 17struct pci_ops;
18struct pci_bus; 18struct pci_bus;
19struct device;
19 20
20struct hw_pci { 21struct hw_pci {
21#ifdef CONFIG_PCI_DOMAINS 22#ifdef CONFIG_PCI_DOMAINS
@@ -68,7 +69,16 @@ struct pci_sys_data {
68/* 69/*
69 * Call this with your hw_pci struct to initialise the PCI system. 70 * Call this with your hw_pci struct to initialise the PCI system.
70 */ 71 */
71void pci_common_init(struct hw_pci *); 72void pci_common_init_dev(struct device *, struct hw_pci *);
73
74/*
75 * Compatibility wrapper for older platforms that do not care about
76 * passing the parent device.
77 */
78static inline void pci_common_init(struct hw_pci *hw)
79{
80 pci_common_init_dev(NULL, hw);
81}
72 82
73/* 83/*
74 * Setup early fixed I/O mapping. 84 * Setup early fixed I/O mapping.
@@ -96,9 +106,4 @@ extern struct pci_ops via82c505_ops;
96extern int via82c505_setup(int nr, struct pci_sys_data *); 106extern int via82c505_setup(int nr, struct pci_sys_data *);
97extern void via82c505_init(void *sysdata); 107extern void via82c505_init(void *sysdata);
98 108
99extern struct pci_ops pci_v3_ops;
100extern int pci_v3_setup(int nr, struct pci_sys_data *);
101extern void pci_v3_preinit(void);
102extern void pci_v3_postinit(void);
103
104#endif /* __ASM_MACH_PCI_H */ 109#endif /* __ASM_MACH_PCI_H */
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index ce0dbe7c1625..c4ae171850f8 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -32,5 +32,14 @@ struct psci_operations {
32}; 32};
33 33
34extern struct psci_operations psci_ops; 34extern struct psci_operations psci_ops;
35extern struct smp_operations psci_smp_ops;
36
37#ifdef CONFIG_ARM_PSCI
38void psci_init(void);
39bool psci_smp_available(void);
40#else
41static inline void psci_init(void) { }
42static inline bool psci_smp_available(void) { return false; }
43#endif
35 44
36#endif /* __ASM_ARM_PSCI_H */ 45#endif /* __ASM_ARM_PSCI_H */
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 3d52ee1bfb31..04c99f36ff7f 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -45,6 +45,7 @@ struct pt_regs {
45 */ 45 */
46static inline int valid_user_regs(struct pt_regs *regs) 46static inline int valid_user_regs(struct pt_regs *regs)
47{ 47{
48#ifndef CONFIG_CPU_V7M
48 unsigned long mode = regs->ARM_cpsr & MODE_MASK; 49 unsigned long mode = regs->ARM_cpsr & MODE_MASK;
49 50
50 /* 51 /*
@@ -67,6 +68,9 @@ static inline int valid_user_regs(struct pt_regs *regs)
67 regs->ARM_cpsr |= USR_MODE; 68 regs->ARM_cpsr |= USR_MODE;
68 69
69 return 0; 70 return 0;
71#else /* ifndef CONFIG_CPU_V7M */
72 return 1;
73#endif
70} 74}
71 75
72static inline long regs_return_value(struct pt_regs *regs) 76static inline long regs_return_value(struct pt_regs *regs)
diff --git a/arch/arm/include/asm/system_info.h b/arch/arm/include/asm/system_info.h
index dfd386d0c022..720ea0320a6d 100644
--- a/arch/arm/include/asm/system_info.h
+++ b/arch/arm/include/asm/system_info.h
@@ -11,6 +11,7 @@
11#define CPU_ARCH_ARMv5TEJ 7 11#define CPU_ARCH_ARMv5TEJ 7
12#define CPU_ARCH_ARMv6 8 12#define CPU_ARCH_ARMv6 8
13#define CPU_ARCH_ARMv7 9 13#define CPU_ARCH_ARMv7 9
14#define CPU_ARCH_ARMv7M 10
14 15
15#ifndef __ASSEMBLY__ 16#ifndef __ASSEMBLY__
16 17
diff --git a/arch/arm/include/asm/v7m.h b/arch/arm/include/asm/v7m.h
new file mode 100644
index 000000000000..fa88d09fa3d9
--- /dev/null
+++ b/arch/arm/include/asm/v7m.h
@@ -0,0 +1,44 @@
1/*
2 * Common defines for v7m cpus
3 */
4#define V7M_SCS_ICTR IOMEM(0xe000e004)
5#define V7M_SCS_ICTR_INTLINESNUM_MASK 0x0000000f
6
7#define BASEADDR_V7M_SCB IOMEM(0xe000ed00)
8
9#define V7M_SCB_CPUID 0x00
10
11#define V7M_SCB_ICSR 0x04
12#define V7M_SCB_ICSR_PENDSVSET (1 << 28)
13#define V7M_SCB_ICSR_PENDSVCLR (1 << 27)
14#define V7M_SCB_ICSR_RETTOBASE (1 << 11)
15
16#define V7M_SCB_VTOR 0x08
17
18#define V7M_SCB_SCR 0x10
19#define V7M_SCB_SCR_SLEEPDEEP (1 << 2)
20
21#define V7M_SCB_CCR 0x14
22#define V7M_SCB_CCR_STKALIGN (1 << 9)
23
24#define V7M_SCB_SHPR2 0x1c
25#define V7M_SCB_SHPR3 0x20
26
27#define V7M_SCB_SHCSR 0x24
28#define V7M_SCB_SHCSR_USGFAULTENA (1 << 18)
29#define V7M_SCB_SHCSR_BUSFAULTENA (1 << 17)
30#define V7M_SCB_SHCSR_MEMFAULTENA (1 << 16)
31
32#define V7M_xPSR_FRAMEPTRALIGN 0x00000200
33#define V7M_xPSR_EXCEPTIONNO 0x000001ff
34
35/*
36 * When branching to an address that has bits [31:28] == 0xf an exception return
37 * occurs. Bits [27:5] are reserved (SBOP). If the processor implements the FP
38 * extension Bit [4] defines if the exception frame has space allocated for FP
39 * state information, SBOP otherwise. Bit [3] defines the mode that is returned
40 * to (0 -> handler mode; 1 -> thread mode). Bit [2] defines which sp is used
41 * (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01.
42 */
43#define EXC_RET_STACK_MASK 0x00000004
44#define EXC_RET_THREADMODE_PROCESSSTACK 0xfffffffd
diff --git a/arch/arm/include/debug/imx-uart.h b/arch/arm/include/debug/imx-uart.h
index 91d38e38a0b4..29da84e183f4 100644
--- a/arch/arm/include/debug/imx-uart.h
+++ b/arch/arm/include/debug/imx-uart.h
@@ -65,6 +65,14 @@
65#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR 65#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR
66#define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n) 66#define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n)
67 67
68#define IMX6SL_UART1_BASE_ADDR 0x02020000
69#define IMX6SL_UART2_BASE_ADDR 0x02024000
70#define IMX6SL_UART3_BASE_ADDR 0x02034000
71#define IMX6SL_UART4_BASE_ADDR 0x02038000
72#define IMX6SL_UART5_BASE_ADDR 0x02018000
73#define IMX6SL_UART_BASE_ADDR(n) IMX6SL_UART##n##_BASE_ADDR
74#define IMX6SL_UART_BASE(n) IMX6SL_UART_BASE_ADDR(n)
75
68#define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT) 76#define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT)
69 77
70#ifdef CONFIG_DEBUG_IMX1_UART 78#ifdef CONFIG_DEBUG_IMX1_UART
@@ -83,6 +91,8 @@
83#define UART_PADDR IMX_DEBUG_UART_BASE(IMX53) 91#define UART_PADDR IMX_DEBUG_UART_BASE(IMX53)
84#elif defined(CONFIG_DEBUG_IMX6Q_UART) 92#elif defined(CONFIG_DEBUG_IMX6Q_UART)
85#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6Q) 93#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6Q)
94#elif defined(CONFIG_DEBUG_IMX6SL_UART)
95#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SL)
86#endif 96#endif
87 97
88#endif /* __DEBUG_IMX_UART_H */ 98#endif /* __DEBUG_IMX_UART_H */
diff --git a/arch/arm/include/debug/keystone.S b/arch/arm/include/debug/keystone.S
new file mode 100644
index 000000000000..9aef9ba3f4f0
--- /dev/null
+++ b/arch/arm/include/debug/keystone.S
@@ -0,0 +1,43 @@
1/*
2 * Early serial debug output macro for Keystone SOCs
3 *
4 * Copyright 2013 Texas Instruments, Inc.
5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 *
7 * Based on RMKs low level debug code.
8 * Copyright (C) 1994-1999 Russell King
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/serial_reg.h>
16
17#define UART_SHIFT 2
18#if defined(CONFIG_DEBUG_KEYSTONE_UART0)
19#define UART_PHYS 0x02530c00
20#define UART_VIRT 0xfeb30c00
21#elif defined(CONFIG_DEBUG_KEYSTONE_UART1)
22#define UART_PHYS 0x02531000
23#define UART_VIRT 0xfeb31000
24#endif
25
26 .macro addruart, rp, rv, tmp
27 ldr \rv, =UART_VIRT @ physical base address
28 ldr \rp, =UART_PHYS @ virtual base address
29 .endm
30
31 .macro senduart,rd,rx
32 str \rd, [\rx, #UART_TX << UART_SHIFT]
33 .endm
34
35 .macro busyuart,rd,rx
361002: ldr \rd, [\rx, #UART_LSR << UART_SHIFT]
37 and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
38 teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
39 bne 1002b
40 .endm
41
42 .macro waituart,rd,rx
43 .endm
diff --git a/arch/arm/include/debug/mvebu.S b/arch/arm/include/debug/mvebu.S
index df191afa3be1..6517311a1c91 100644
--- a/arch/arm/include/debug/mvebu.S
+++ b/arch/arm/include/debug/mvebu.S
@@ -11,7 +11,12 @@
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12*/ 12*/
13 13
14#ifdef CONFIG_DEBUG_MVEBU_UART_ALTERNATE
15#define ARMADA_370_XP_REGS_PHYS_BASE 0xf1000000
16#else
14#define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000 17#define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000
18#endif
19
15#define ARMADA_370_XP_REGS_VIRT_BASE 0xfec00000 20#define ARMADA_370_XP_REGS_VIRT_BASE 0xfec00000
16 21
17 .macro addruart, rp, rv, tmp 22 .macro addruart, rp, rv, tmp
diff --git a/arch/arm/include/debug/rockchip.S b/arch/arm/include/debug/rockchip.S
new file mode 100644
index 000000000000..cfd883e69588
--- /dev/null
+++ b/arch/arm/include/debug/rockchip.S
@@ -0,0 +1,42 @@
1/*
2 * Early serial output macro for Rockchip SoCs
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#if defined(CONFIG_DEBUG_RK29_UART0)
14#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20060000
15#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed60000
16#elif defined(CONFIG_DEBUG_RK29_UART1)
17#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20064000
18#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed64000
19#elif defined(CONFIG_DEBUG_RK29_UART2)
20#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20068000
21#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed68000
22#elif defined(CONFIG_DEBUG_RK3X_UART0)
23#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x10124000
24#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfeb24000
25#elif defined(CONFIG_DEBUG_RK3X_UART1)
26#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x10126000
27#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfeb26000
28#elif defined(CONFIG_DEBUG_RK3X_UART2)
29#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20064000
30#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed64000
31#elif defined(CONFIG_DEBUG_RK3X_UART3)
32#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20068000
33#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed68000
34#endif
35
36 .macro addruart, rp, rv, tmp
37 ldr \rp, =ROCKCHIP_UART_DEBUG_PHYS_BASE
38 ldr \rv, =ROCKCHIP_UART_DEBUG_VIRT_BASE
39 .endm
40
41#define UART_SHIFT 2
42#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/include/debug/u300.S b/arch/arm/include/debug/u300.S
new file mode 100644
index 000000000000..6f04f08a203c
--- /dev/null
+++ b/arch/arm/include/debug/u300.S
@@ -0,0 +1,18 @@
1/*
2 * Copyright (C) 2006-2013 ST-Ericsson AB
3 * License terms: GNU General Public License (GPL) version 2
4 * Debugging macro include header.
5 * Author: Linus Walleij <linus.walleij@stericsson.com>
6 */
7#define U300_SLOW_PER_PHYS_BASE 0xc0010000
8#define U300_SLOW_PER_VIRT_BASE 0xff000000
9
10 .macro addruart, rp, rv, tmp
11 /* If we move the address using MMU, use this. */
12 ldr \rp, = U300_SLOW_PER_PHYS_BASE @ MMU off, physical address
13 ldr \rv, = U300_SLOW_PER_VIRT_BASE @ MMU on, virtual address
14 orr \rp, \rp, #0x00003000
15 orr \rv, \rv, #0x00003000
16 .endm
17
18#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/include/uapi/asm/ptrace.h b/arch/arm/include/uapi/asm/ptrace.h
index 96ee0929790f..5af0ed1b825a 100644
--- a/arch/arm/include/uapi/asm/ptrace.h
+++ b/arch/arm/include/uapi/asm/ptrace.h
@@ -34,28 +34,47 @@
34 34
35/* 35/*
36 * PSR bits 36 * PSR bits
37 * Note on V7M there is no mode contained in the PSR
37 */ 38 */
38#define USR26_MODE 0x00000000 39#define USR26_MODE 0x00000000
39#define FIQ26_MODE 0x00000001 40#define FIQ26_MODE 0x00000001
40#define IRQ26_MODE 0x00000002 41#define IRQ26_MODE 0x00000002
41#define SVC26_MODE 0x00000003 42#define SVC26_MODE 0x00000003
43#if defined(__KERNEL__) && defined(CONFIG_CPU_V7M)
44/*
45 * Use 0 here to get code right that creates a userspace
46 * or kernel space thread.
47 */
48#define USR_MODE 0x00000000
49#define SVC_MODE 0x00000000
50#else
42#define USR_MODE 0x00000010 51#define USR_MODE 0x00000010
52#define SVC_MODE 0x00000013
53#endif
43#define FIQ_MODE 0x00000011 54#define FIQ_MODE 0x00000011
44#define IRQ_MODE 0x00000012 55#define IRQ_MODE 0x00000012
45#define SVC_MODE 0x00000013
46#define ABT_MODE 0x00000017 56#define ABT_MODE 0x00000017
47#define HYP_MODE 0x0000001a 57#define HYP_MODE 0x0000001a
48#define UND_MODE 0x0000001b 58#define UND_MODE 0x0000001b
49#define SYSTEM_MODE 0x0000001f 59#define SYSTEM_MODE 0x0000001f
50#define MODE32_BIT 0x00000010 60#define MODE32_BIT 0x00000010
51#define MODE_MASK 0x0000001f 61#define MODE_MASK 0x0000001f
52#define PSR_T_BIT 0x00000020 62
53#define PSR_F_BIT 0x00000040 63#define V4_PSR_T_BIT 0x00000020 /* >= V4T, but not V7M */
54#define PSR_I_BIT 0x00000080 64#define V7M_PSR_T_BIT 0x01000000
55#define PSR_A_BIT 0x00000100 65#if defined(__KERNEL__) && defined(CONFIG_CPU_V7M)
56#define PSR_E_BIT 0x00000200 66#define PSR_T_BIT V7M_PSR_T_BIT
57#define PSR_J_BIT 0x01000000 67#else
58#define PSR_Q_BIT 0x08000000 68/* for compatibility */
69#define PSR_T_BIT V4_PSR_T_BIT
70#endif
71
72#define PSR_F_BIT 0x00000040 /* >= V4, but not V7M */
73#define PSR_I_BIT 0x00000080 /* >= V4, but not V7M */
74#define PSR_A_BIT 0x00000100 /* >= V6, but not V7M */
75#define PSR_E_BIT 0x00000200 /* >= V6, but not V7M */
76#define PSR_J_BIT 0x01000000 /* >= V5J, but not V7M */
77#define PSR_Q_BIT 0x08000000 /* >= V5E, including V7M */
59#define PSR_V_BIT 0x10000000 78#define PSR_V_BIT 0x10000000
60#define PSR_C_BIT 0x20000000 79#define PSR_C_BIT 0x20000000
61#define PSR_Z_BIT 0x40000000 80#define PSR_Z_BIT 0x40000000
generated by cgit v1.2.2 (git 2.25.0) at 2026-05-29 22:46:36 -0400