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author | Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | 2009-03-25 04:58:47 -0400 |
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committer | Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | 2009-03-25 04:58:47 -0400 |
commit | bba7d0b9ba0f04d25145de8170a17a3a07bbfdde (patch) | |
tree | e832a36e27088294753953a307ed1fb215ef171b /arch/arm/include | |
parent | 8e0ee43bc2c3e19db56a4adaa9a9b04ce885cd84 (diff) |
ARM: tlbflush.h: introduce TLB_BTB flag
Signed-off-by: Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
Diffstat (limited to 'arch/arm/include')
-rw-r--r-- | arch/arm/include/asm/tlbflush.h | 19 |
1 files changed, 6 insertions, 13 deletions
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h index b543a054a17e..ffedd2494eab 100644 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h | |||
@@ -39,6 +39,7 @@ | |||
39 | #define TLB_V6_D_ASID (1 << 17) | 39 | #define TLB_V6_D_ASID (1 << 17) |
40 | #define TLB_V6_I_ASID (1 << 18) | 40 | #define TLB_V6_I_ASID (1 << 18) |
41 | 41 | ||
42 | #define TLB_BTB (1 << 28) | ||
42 | #define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */ | 43 | #define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */ |
43 | #define TLB_DCLEAN (1 << 30) | 44 | #define TLB_DCLEAN (1 << 30) |
44 | #define TLB_WB (1 << 31) | 45 | #define TLB_WB (1 << 31) |
@@ -140,7 +141,7 @@ | |||
140 | # define v4wb_always_flags (-1UL) | 141 | # define v4wb_always_flags (-1UL) |
141 | #endif | 142 | #endif |
142 | 143 | ||
143 | #define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | \ | 144 | #define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \ |
144 | TLB_V6_I_FULL | TLB_V6_D_FULL | \ | 145 | TLB_V6_I_FULL | TLB_V6_D_FULL | \ |
145 | TLB_V6_I_PAGE | TLB_V6_D_PAGE | \ | 146 | TLB_V6_I_PAGE | TLB_V6_D_PAGE | \ |
146 | TLB_V6_I_ASID | TLB_V6_D_ASID) | 147 | TLB_V6_I_ASID | TLB_V6_D_ASID) |
@@ -297,9 +298,7 @@ static inline void local_flush_tlb_all(void) | |||
297 | if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL)) | 298 | if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL)) |
298 | asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); | 299 | asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); |
299 | 300 | ||
300 | if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL | | 301 | if (tlb_flag(TLB_BTB)) { |
301 | TLB_V6_I_PAGE | TLB_V6_D_PAGE | | ||
302 | TLB_V6_I_ASID | TLB_V6_D_ASID)) { | ||
303 | /* flush the branch target cache */ | 302 | /* flush the branch target cache */ |
304 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); | 303 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); |
305 | dsb(); | 304 | dsb(); |
@@ -334,9 +333,7 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm) | |||
334 | if (tlb_flag(TLB_V6_I_ASID)) | 333 | if (tlb_flag(TLB_V6_I_ASID)) |
335 | asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc"); | 334 | asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc"); |
336 | 335 | ||
337 | if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL | | 336 | if (tlb_flag(TLB_BTB)) { |
338 | TLB_V6_I_PAGE | TLB_V6_D_PAGE | | ||
339 | TLB_V6_I_ASID | TLB_V6_D_ASID)) { | ||
340 | /* flush the branch target cache */ | 337 | /* flush the branch target cache */ |
341 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); | 338 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); |
342 | dsb(); | 339 | dsb(); |
@@ -374,9 +371,7 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) | |||
374 | if (tlb_flag(TLB_V6_I_PAGE)) | 371 | if (tlb_flag(TLB_V6_I_PAGE)) |
375 | asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc"); | 372 | asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc"); |
376 | 373 | ||
377 | if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL | | 374 | if (tlb_flag(TLB_BTB)) { |
378 | TLB_V6_I_PAGE | TLB_V6_D_PAGE | | ||
379 | TLB_V6_I_ASID | TLB_V6_D_ASID)) { | ||
380 | /* flush the branch target cache */ | 375 | /* flush the branch target cache */ |
381 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); | 376 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); |
382 | dsb(); | 377 | dsb(); |
@@ -411,9 +406,7 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr) | |||
411 | if (tlb_flag(TLB_V6_I_PAGE)) | 406 | if (tlb_flag(TLB_V6_I_PAGE)) |
412 | asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc"); | 407 | asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc"); |
413 | 408 | ||
414 | if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL | | 409 | if (tlb_flag(TLB_BTB)) { |
415 | TLB_V6_I_PAGE | TLB_V6_D_PAGE | | ||
416 | TLB_V6_I_ASID | TLB_V6_D_ASID)) { | ||
417 | /* flush the branch target cache */ | 410 | /* flush the branch target cache */ |
418 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); | 411 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); |
419 | dsb(); | 412 | dsb(); |