diff options
author | Alexander Shishkin <virtuoso@slind.org> | 2010-08-04 06:25:20 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-08-10 17:10:53 -0400 |
commit | 9e354ea8e0710baf05804168fdabe90231b3d363 (patch) | |
tree | 3f86f2e6c8b7fd08256d9a2496583d0a21c51a05 /arch/arm/include | |
parent | 686ff22812d908eaa537edd62fb1eb3d64336301 (diff) |
ARM: 6292/1: coresight: add ETM management registers
Add notion of ETM OS lock, save and restore registers.
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Alexander Shishkin <virtuoso@slind.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/include')
-rw-r--r-- | arch/arm/include/asm/hardware/coresight.h | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/include/asm/hardware/coresight.h b/arch/arm/include/asm/hardware/coresight.h index f82b25d4f73e..212e47828c79 100644 --- a/arch/arm/include/asm/hardware/coresight.h +++ b/arch/arm/include/asm/hardware/coresight.h | |||
@@ -48,8 +48,6 @@ struct tracectx { | |||
48 | /* CoreSight Component Registers */ | 48 | /* CoreSight Component Registers */ |
49 | #define CSCR_CLASS 0xff4 | 49 | #define CSCR_CLASS 0xff4 |
50 | 50 | ||
51 | #define CSCR_PRSR 0x314 | ||
52 | |||
53 | #define UNLOCK_MAGIC 0xc5acce55 | 51 | #define UNLOCK_MAGIC 0xc5acce55 |
54 | 52 | ||
55 | /* ETM control register, "ETM Architecture", 3.3.1 */ | 53 | /* ETM control register, "ETM Architecture", 3.3.1 */ |
@@ -132,6 +130,12 @@ struct tracectx { | |||
132 | ETMCTRL_BRANCH_OUTPUT | \ | 130 | ETMCTRL_BRANCH_OUTPUT | \ |
133 | ETMCTRL_DO_CONTEXTID) | 131 | ETMCTRL_DO_CONTEXTID) |
134 | 132 | ||
133 | /* ETM management registers, "ETM Architecture", 3.5.24 */ | ||
134 | #define ETMMR_OSLAR 0x300 | ||
135 | #define ETMMR_OSLSR 0x304 | ||
136 | #define ETMMR_OSSRR 0x308 | ||
137 | #define ETMMR_PDSR 0x314 | ||
138 | |||
135 | /* ETB registers, "CoreSight Components TRM", 9.3 */ | 139 | /* ETB registers, "CoreSight Components TRM", 9.3 */ |
136 | #define ETBR_DEPTH 0x04 | 140 | #define ETBR_DEPTH 0x04 |
137 | #define ETBR_STATUS 0x0c | 141 | #define ETBR_STATUS 0x0c |