diff options
author | Catalin Marinas <catalin.marinas@arm.com> | 2010-09-13 10:58:06 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-09-19 07:17:44 -0400 |
commit | 6012191aa9c6ffff3a23b81162298318b56d7cb3 (patch) | |
tree | 8f08d869b452d66f126743bcfd73aa6f5a701605 /arch/arm/include | |
parent | c01778001a4f5ad9c62d882776235f3f31922fdd (diff) |
ARM: 6380/1: Introduce __sync_icache_dcache() for VIPT caches
On SMP systems, there is a small chance of a PTE becoming visible to a
different CPU before the current cache maintenance operations in
update_mmu_cache(). To avoid this, cache maintenance must be handled in
set_pte_at() (similar to IA-64 and PowerPC).
This patch provides a unified VIPT cache handling mechanism and
implements the __sync_icache_dcache() function for ARMv6 onwards
architectures. It is called from set_pte_at() and replaces the
update_mmu_cache(). The latter is still used on VIVT hardware where a
vm_area_struct is required.
Tested-by: Rabin Vincent <rabin.vincent@stericsson.com>
Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/include')
-rw-r--r-- | arch/arm/include/asm/pgtable.h | 26 | ||||
-rw-r--r-- | arch/arm/include/asm/tlbflush.h | 10 |
2 files changed, 32 insertions, 4 deletions
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h index ab68cf1ef80f..42e694f1d58e 100644 --- a/arch/arm/include/asm/pgtable.h +++ b/arch/arm/include/asm/pgtable.h | |||
@@ -278,9 +278,24 @@ extern struct page *empty_zero_page; | |||
278 | 278 | ||
279 | #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext) | 279 | #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext) |
280 | 280 | ||
281 | #define set_pte_at(mm,addr,ptep,pteval) do { \ | 281 | #if __LINUX_ARM_ARCH__ < 6 |
282 | set_pte_ext(ptep, pteval, (addr) >= TASK_SIZE ? 0 : PTE_EXT_NG); \ | 282 | static inline void __sync_icache_dcache(pte_t pteval) |
283 | } while (0) | 283 | { |
284 | } | ||
285 | #else | ||
286 | extern void __sync_icache_dcache(pte_t pteval); | ||
287 | #endif | ||
288 | |||
289 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, | ||
290 | pte_t *ptep, pte_t pteval) | ||
291 | { | ||
292 | if (addr >= TASK_SIZE) | ||
293 | set_pte_ext(ptep, pteval, 0); | ||
294 | else { | ||
295 | __sync_icache_dcache(pteval); | ||
296 | set_pte_ext(ptep, pteval, PTE_EXT_NG); | ||
297 | } | ||
298 | } | ||
284 | 299 | ||
285 | /* | 300 | /* |
286 | * The following only work if pte_present() is true. | 301 | * The following only work if pte_present() is true. |
@@ -290,8 +305,13 @@ extern struct page *empty_zero_page; | |||
290 | #define pte_write(pte) (pte_val(pte) & L_PTE_WRITE) | 305 | #define pte_write(pte) (pte_val(pte) & L_PTE_WRITE) |
291 | #define pte_dirty(pte) (pte_val(pte) & L_PTE_DIRTY) | 306 | #define pte_dirty(pte) (pte_val(pte) & L_PTE_DIRTY) |
292 | #define pte_young(pte) (pte_val(pte) & L_PTE_YOUNG) | 307 | #define pte_young(pte) (pte_val(pte) & L_PTE_YOUNG) |
308 | #define pte_exec(pte) (pte_val(pte) & L_PTE_EXEC) | ||
293 | #define pte_special(pte) (0) | 309 | #define pte_special(pte) (0) |
294 | 310 | ||
311 | #define pte_present_user(pte) \ | ||
312 | ((pte_val(pte) & (L_PTE_PRESENT | L_PTE_USER)) == \ | ||
313 | (L_PTE_PRESENT | L_PTE_USER)) | ||
314 | |||
295 | #define PTE_BIT_FUNC(fn,op) \ | 315 | #define PTE_BIT_FUNC(fn,op) \ |
296 | static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; } | 316 | static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; } |
297 | 317 | ||
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h index 9ad329ad7458..989c9e57d92b 100644 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h | |||
@@ -562,10 +562,18 @@ extern void flush_tlb_kernel_range(unsigned long start, unsigned long end); | |||
562 | /* | 562 | /* |
563 | * If PG_dcache_clean is not set for the page, we need to ensure that any | 563 | * If PG_dcache_clean is not set for the page, we need to ensure that any |
564 | * cache entries for the kernels virtual memory range are written | 564 | * cache entries for the kernels virtual memory range are written |
565 | * back to the page. | 565 | * back to the page. On ARMv6 and later, the cache coherency is handled via |
566 | * the set_pte_at() function. | ||
566 | */ | 567 | */ |
568 | #if __LINUX_ARM_ARCH__ < 6 | ||
567 | extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, | 569 | extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, |
568 | pte_t *ptep); | 570 | pte_t *ptep); |
571 | #else | ||
572 | static inline void update_mmu_cache(struct vm_area_struct *vma, | ||
573 | unsigned long addr, pte_t *ptep) | ||
574 | { | ||
575 | } | ||
576 | #endif | ||
569 | 577 | ||
570 | #endif | 578 | #endif |
571 | 579 | ||