Merge master.kernel.org:/home/rmk/linux-2.6-arm

* master.kernel.org:/home/rmk/linux-2.6-arm:
  VIDEO: amba clcd: don't disable an already disabled clock
  ARM: Tighten check for allowable CPSR values
  ARM: 6329/1: wire up sys_accept4() on ARM
  ARM: 6328/1: Build with -fno-dwarf2-cfi-asm
  ARM: 6326/1: kgdb: fix GDB_MAX_REGS no longer used

2 files changed, 14 insertions, 4 deletions

diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index c974be8913a7..7ce15eb15f72 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -158,15 +158,24 @@ struct pt_regs {
  */
 static inline int valid_user_regs(struct pt_regs *regs)
 {
-        if (user_mode(regs) && (regs->ARM_cpsr & PSR_I_BIT) == 0) {
-                regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT);
-                return 1;
+        unsigned long mode = regs->ARM_cpsr & MODE_MASK;
+
+        /*
+         * Always clear the F (FIQ) and A (delayed abort) bits
+         */
+        regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT);
+
+        if ((regs->ARM_cpsr & PSR_I_BIT) == 0) {
+                if (mode == USR_MODE)
+                        return 1;
+                if (elf_hwcap & HWCAP_26BIT && mode == USR26_MODE)
+                        return 1;
         }
 
         /*
          * Force CPSR to something logical...
          */
-        regs->ARM_cpsr &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | PSR_T_BIT | MODE32_BIT;
+        regs->ARM_cpsr &= PSR_f | PSR_s | PSR_x | PSR_T_BIT | MODE32_BIT;
         if (!(elf_hwcap & HWCAP_26BIT))
                 regs->ARM_cpsr |= USR_MODE;
 
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index dd2bf53000fe..d02cfb683487 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -392,6 +392,7 @@
 #define __NR_rt_tgsigqueueinfo          (__NR_SYSCALL_BASE+363)
 #define __NR_perf_event_open            (__NR_SYSCALL_BASE+364)
 #define __NR_recvmmsg                   (__NR_SYSCALL_BASE+365)
+#define __NR_accept4                    (__NR_SYSCALL_BASE+366)
 
 /*
  * The following SWIs are ARM private.