diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2009-06-11 10:35:00 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-06-11 10:35:00 -0400 |
commit | 42578c82e0f1810a07ebe29cb05e874893243d8c (patch) | |
tree | e2a3811677d3594e891fc82c940438f6b6abc3e0 /arch/arm/include/asm/tlbflush.h | |
parent | 2631182bf93919577730e6a6c4345308db590057 (diff) | |
parent | 85d6943af50537d3aec58b967ffbd3fec88453e9 (diff) |
Merge branch 'for-rmk' of git://linux-arm.org/linux-2.6 into devel
Conflicts:
arch/arm/Kconfig
arch/arm/kernel/smp.c
arch/arm/mach-realview/Makefile
arch/arm/mach-realview/platsmp.c
Diffstat (limited to 'arch/arm/include/asm/tlbflush.h')
-rw-r--r-- | arch/arm/include/asm/tlbflush.h | 26 |
1 files changed, 24 insertions, 2 deletions
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h index a62218013c78..c964f3fc3bc5 100644 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h | |||
@@ -40,6 +40,12 @@ | |||
40 | #define TLB_V6_I_ASID (1 << 18) | 40 | #define TLB_V6_I_ASID (1 << 18) |
41 | 41 | ||
42 | #define TLB_BTB (1 << 28) | 42 | #define TLB_BTB (1 << 28) |
43 | |||
44 | /* Unified Inner Shareable TLB operations (ARMv7 MP extensions) */ | ||
45 | #define TLB_V7_UIS_PAGE (1 << 19) | ||
46 | #define TLB_V7_UIS_FULL (1 << 20) | ||
47 | #define TLB_V7_UIS_ASID (1 << 21) | ||
48 | |||
43 | #define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */ | 49 | #define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */ |
44 | #define TLB_DCLEAN (1 << 30) | 50 | #define TLB_DCLEAN (1 << 30) |
45 | #define TLB_WB (1 << 31) | 51 | #define TLB_WB (1 << 31) |
@@ -176,9 +182,17 @@ | |||
176 | # define v6wbi_always_flags (-1UL) | 182 | # define v6wbi_always_flags (-1UL) |
177 | #endif | 183 | #endif |
178 | 184 | ||
185 | #ifdef CONFIG_SMP | ||
186 | #define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \ | ||
187 | TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID) | ||
188 | #else | ||
189 | #define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \ | ||
190 | TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID) | ||
191 | #endif | ||
192 | |||
179 | #ifdef CONFIG_CPU_TLB_V7 | 193 | #ifdef CONFIG_CPU_TLB_V7 |
180 | # define v7wbi_possible_flags v6wbi_tlb_flags | 194 | # define v7wbi_possible_flags v7wbi_tlb_flags |
181 | # define v7wbi_always_flags v6wbi_tlb_flags | 195 | # define v7wbi_always_flags v7wbi_tlb_flags |
182 | # ifdef _TLB | 196 | # ifdef _TLB |
183 | # define MULTI_TLB 1 | 197 | # define MULTI_TLB 1 |
184 | # else | 198 | # else |
@@ -316,6 +330,8 @@ static inline void local_flush_tlb_all(void) | |||
316 | asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc"); | 330 | asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc"); |
317 | if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL)) | 331 | if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL)) |
318 | asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); | 332 | asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); |
333 | if (tlb_flag(TLB_V7_UIS_FULL)) | ||
334 | asm("mcr p15, 0, %0, c8, c3, 0" : : "r" (zero) : "cc"); | ||
319 | 335 | ||
320 | if (tlb_flag(TLB_BTB)) { | 336 | if (tlb_flag(TLB_BTB)) { |
321 | /* flush the branch target cache */ | 337 | /* flush the branch target cache */ |
@@ -351,6 +367,8 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm) | |||
351 | asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc"); | 367 | asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc"); |
352 | if (tlb_flag(TLB_V6_I_ASID)) | 368 | if (tlb_flag(TLB_V6_I_ASID)) |
353 | asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc"); | 369 | asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc"); |
370 | if (tlb_flag(TLB_V7_UIS_ASID)) | ||
371 | asm("mcr p15, 0, %0, c8, c3, 2" : : "r" (asid) : "cc"); | ||
354 | 372 | ||
355 | if (tlb_flag(TLB_BTB)) { | 373 | if (tlb_flag(TLB_BTB)) { |
356 | /* flush the branch target cache */ | 374 | /* flush the branch target cache */ |
@@ -389,6 +407,8 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) | |||
389 | asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc"); | 407 | asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc"); |
390 | if (tlb_flag(TLB_V6_I_PAGE)) | 408 | if (tlb_flag(TLB_V6_I_PAGE)) |
391 | asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc"); | 409 | asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc"); |
410 | if (tlb_flag(TLB_V7_UIS_PAGE)) | ||
411 | asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (uaddr) : "cc"); | ||
392 | 412 | ||
393 | if (tlb_flag(TLB_BTB)) { | 413 | if (tlb_flag(TLB_BTB)) { |
394 | /* flush the branch target cache */ | 414 | /* flush the branch target cache */ |
@@ -424,6 +444,8 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr) | |||
424 | asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc"); | 444 | asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc"); |
425 | if (tlb_flag(TLB_V6_I_PAGE)) | 445 | if (tlb_flag(TLB_V6_I_PAGE)) |
426 | asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc"); | 446 | asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc"); |
447 | if (tlb_flag(TLB_V7_UIS_PAGE)) | ||
448 | asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (kaddr) : "cc"); | ||
427 | 449 | ||
428 | if (tlb_flag(TLB_BTB)) { | 450 | if (tlb_flag(TLB_BTB)) { |
429 | /* flush the branch target cache */ | 451 | /* flush the branch target cache */ |