diff options
author | Takashi Iwai <tiwai@suse.de> | 2013-04-25 07:02:35 -0400 |
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committer | Takashi Iwai <tiwai@suse.de> | 2013-04-25 07:02:35 -0400 |
commit | 2fc565e4eaf8fc633bfc741b90e1f28dba732ee1 (patch) | |
tree | 98c994692f84aee07cf1c7b4cda245ae5235a94d /arch/arm/include/asm/tlbflush.h | |
parent | 7fc7d047216aa4923d401c637be2ebc6e3d5bd9b (diff) | |
parent | 5cc50fc858a5ab37dc2744d72d7ffed96f23afd8 (diff) |
Merge tag 'asoc-v3.10-3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-next
ASoC: More updates for v3.10
A few more fixes, nothing too major though the DMA changes fix modular
builds.
Diffstat (limited to 'arch/arm/include/asm/tlbflush.h')
-rw-r--r-- | arch/arm/include/asm/tlbflush.h | 11 |
1 files changed, 2 insertions, 9 deletions
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h index 9e9c041358ca..ab865e65a84c 100644 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h | |||
@@ -14,7 +14,6 @@ | |||
14 | 14 | ||
15 | #include <asm/glue.h> | 15 | #include <asm/glue.h> |
16 | 16 | ||
17 | #define TLB_V3_PAGE (1 << 0) | ||
18 | #define TLB_V4_U_PAGE (1 << 1) | 17 | #define TLB_V4_U_PAGE (1 << 1) |
19 | #define TLB_V4_D_PAGE (1 << 2) | 18 | #define TLB_V4_D_PAGE (1 << 2) |
20 | #define TLB_V4_I_PAGE (1 << 3) | 19 | #define TLB_V4_I_PAGE (1 << 3) |
@@ -22,7 +21,6 @@ | |||
22 | #define TLB_V6_D_PAGE (1 << 5) | 21 | #define TLB_V6_D_PAGE (1 << 5) |
23 | #define TLB_V6_I_PAGE (1 << 6) | 22 | #define TLB_V6_I_PAGE (1 << 6) |
24 | 23 | ||
25 | #define TLB_V3_FULL (1 << 8) | ||
26 | #define TLB_V4_U_FULL (1 << 9) | 24 | #define TLB_V4_U_FULL (1 << 9) |
27 | #define TLB_V4_D_FULL (1 << 10) | 25 | #define TLB_V4_D_FULL (1 << 10) |
28 | #define TLB_V4_I_FULL (1 << 11) | 26 | #define TLB_V4_I_FULL (1 << 11) |
@@ -52,7 +50,6 @@ | |||
52 | * ============= | 50 | * ============= |
53 | * | 51 | * |
54 | * We have the following to choose from: | 52 | * We have the following to choose from: |
55 | * v3 - ARMv3 | ||
56 | * v4 - ARMv4 without write buffer | 53 | * v4 - ARMv4 without write buffer |
57 | * v4wb - ARMv4 with write buffer without I TLB flush entry instruction | 54 | * v4wb - ARMv4 with write buffer without I TLB flush entry instruction |
58 | * v4wbi - ARMv4 with write buffer with I TLB flush entry instruction | 55 | * v4wbi - ARMv4 with write buffer with I TLB flush entry instruction |
@@ -330,7 +327,6 @@ static inline void local_flush_tlb_all(void) | |||
330 | if (tlb_flag(TLB_WB)) | 327 | if (tlb_flag(TLB_WB)) |
331 | dsb(); | 328 | dsb(); |
332 | 329 | ||
333 | tlb_op(TLB_V3_FULL, "c6, c0, 0", zero); | ||
334 | tlb_op(TLB_V4_U_FULL | TLB_V6_U_FULL, "c8, c7, 0", zero); | 330 | tlb_op(TLB_V4_U_FULL | TLB_V6_U_FULL, "c8, c7, 0", zero); |
335 | tlb_op(TLB_V4_D_FULL | TLB_V6_D_FULL, "c8, c6, 0", zero); | 331 | tlb_op(TLB_V4_D_FULL | TLB_V6_D_FULL, "c8, c6, 0", zero); |
336 | tlb_op(TLB_V4_I_FULL | TLB_V6_I_FULL, "c8, c5, 0", zero); | 332 | tlb_op(TLB_V4_I_FULL | TLB_V6_I_FULL, "c8, c5, 0", zero); |
@@ -351,9 +347,8 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm) | |||
351 | if (tlb_flag(TLB_WB)) | 347 | if (tlb_flag(TLB_WB)) |
352 | dsb(); | 348 | dsb(); |
353 | 349 | ||
354 | if (possible_tlb_flags & (TLB_V3_FULL|TLB_V4_U_FULL|TLB_V4_D_FULL|TLB_V4_I_FULL)) { | 350 | if (possible_tlb_flags & (TLB_V4_U_FULL|TLB_V4_D_FULL|TLB_V4_I_FULL)) { |
355 | if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) { | 351 | if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) { |
356 | tlb_op(TLB_V3_FULL, "c6, c0, 0", zero); | ||
357 | tlb_op(TLB_V4_U_FULL, "c8, c7, 0", zero); | 352 | tlb_op(TLB_V4_U_FULL, "c8, c7, 0", zero); |
358 | tlb_op(TLB_V4_D_FULL, "c8, c6, 0", zero); | 353 | tlb_op(TLB_V4_D_FULL, "c8, c6, 0", zero); |
359 | tlb_op(TLB_V4_I_FULL, "c8, c5, 0", zero); | 354 | tlb_op(TLB_V4_I_FULL, "c8, c5, 0", zero); |
@@ -385,9 +380,8 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) | |||
385 | if (tlb_flag(TLB_WB)) | 380 | if (tlb_flag(TLB_WB)) |
386 | dsb(); | 381 | dsb(); |
387 | 382 | ||
388 | if (possible_tlb_flags & (TLB_V3_PAGE|TLB_V4_U_PAGE|TLB_V4_D_PAGE|TLB_V4_I_PAGE|TLB_V4_I_FULL) && | 383 | if (possible_tlb_flags & (TLB_V4_U_PAGE|TLB_V4_D_PAGE|TLB_V4_I_PAGE|TLB_V4_I_FULL) && |
389 | cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) { | 384 | cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) { |
390 | tlb_op(TLB_V3_PAGE, "c6, c0, 0", uaddr); | ||
391 | tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", uaddr); | 385 | tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", uaddr); |
392 | tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", uaddr); | 386 | tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", uaddr); |
393 | tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", uaddr); | 387 | tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", uaddr); |
@@ -418,7 +412,6 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr) | |||
418 | if (tlb_flag(TLB_WB)) | 412 | if (tlb_flag(TLB_WB)) |
419 | dsb(); | 413 | dsb(); |
420 | 414 | ||
421 | tlb_op(TLB_V3_PAGE, "c6, c0, 0", kaddr); | ||
422 | tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", kaddr); | 415 | tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", kaddr); |
423 | tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", kaddr); | 416 | tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", kaddr); |
424 | tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", kaddr); | 417 | tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", kaddr); |