Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (236 commits)
  [ARM] 5300/1: fixup spitz reset during boot
  [ARM] 5295/1: make ZONE_DMA optional
  [ARM] 5239/1: Palm Zire 72 power management support
  [ARM] 5298/1: Drop desc_handle_irq()
  [ARM] 5297/1: [KS8695] Fix two compile-time warnings
  [ARM] 5296/1: [KS8695] Replace macro's with trailing underscores.
  [ARM] pxa: allow multi-machine PCMCIA builds
  [ARM] pxa: add preliminary CPUFREQ support for PXA3xx
  [ARM] pxa: add missing ACCR bit definitions to pxa3xx-regs.h
  [ARM] pxa: rename cpu-pxa.c to cpufreq-pxa2xx.c
  [ARM] pxa/zylonite: add support for USB OHCI
  [ARM] ohci-pxa27x: use ioremap() and offset for register access
  [ARM] ohci-pxa27x: introduce pxa27x_clear_otgph()
  [ARM] ohci-pxa27x: use platform_get_{irq,resource} for the resource
  [ARM] ohci-pxa27x: move OHCI controller specific registers into the driver
  [ARM] ohci-pxa27x: introduce flags to avoid direct access to OHCI registers
  [ARM] pxa: move I2S register and bit definitions into pxa2xx-i2s.c
  [ARM] pxa: simplify DMA register definitions
  [ARM] pxa: make additional DCSR bits valid for PXA3xx
  [ARM] pxa: move i2c register and bit definitions into i2c-pxa.c
  ...

Fixed up conflicts in
	arch/arm/mach-versatile/core.c
	sound/soc/pxa/pxa2xx-ac97.c
	sound/soc/pxa/pxa2xx-i2s.c
manually.

1 files changed, 0 insertions, 90 deletions

diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 9073d9c6567e..de6c59f814a1 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -444,94 +444,4 @@ static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt,
         dmac_inv_range(start, start + size);
 }
 
-#define __cacheid_present(val)                  (val != read_cpuid(CPUID_ID))
-#define __cacheid_type_v7(val)                  ((val & (7 << 29)) == (4 << 29))
-
-#define __cacheid_vivt_prev7(val)               ((val & (15 << 25)) != (14 << 25))
-#define __cacheid_vipt_prev7(val)               ((val & (15 << 25)) == (14 << 25))
-#define __cacheid_vipt_nonaliasing_prev7(val)   ((val & (15 << 25 | 1 << 23)) == (14 << 25))
-#define __cacheid_vipt_aliasing_prev7(val)      ((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23))
-
-#define __cacheid_vivt(val)                     (__cacheid_type_v7(val) ? 0 : __cacheid_vivt_prev7(val))
-#define __cacheid_vipt(val)                     (__cacheid_type_v7(val) ? 1 : __cacheid_vipt_prev7(val))
-#define __cacheid_vipt_nonaliasing(val)         (__cacheid_type_v7(val) ? 1 : __cacheid_vipt_nonaliasing_prev7(val))
-#define __cacheid_vipt_aliasing(val)            (__cacheid_type_v7(val) ? 0 : __cacheid_vipt_aliasing_prev7(val))
-#define __cacheid_vivt_asid_tagged_instr(val)   (__cacheid_type_v7(val) ? ((val & (3 << 14)) == (1 << 14)) : 0)
-
-#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
-/*
- * VIVT caches only
- */
-#define cache_is_vivt()                 1
-#define cache_is_vipt()                 0
-#define cache_is_vipt_nonaliasing()     0
-#define cache_is_vipt_aliasing()        0
-#define icache_is_vivt_asid_tagged()    0
-
-#elif !defined(CONFIG_CPU_CACHE_VIVT) && defined(CONFIG_CPU_CACHE_VIPT)
-/*
- * VIPT caches only
- */
-#define cache_is_vivt()                 0
-#define cache_is_vipt()                 1
-#define cache_is_vipt_nonaliasing()                                     \
-        ({                                                              \
-                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
-                __cacheid_vipt_nonaliasing(__val);                      \
-        })
-
-#define cache_is_vipt_aliasing()                                        \
-        ({                                                              \
-                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
-                __cacheid_vipt_aliasing(__val);                         \
-        })
-
-#define icache_is_vivt_asid_tagged()                                    \
-        ({                                                              \
-                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
-                __cacheid_vivt_asid_tagged_instr(__val);                \
-        })
-
-#else
-/*
- * VIVT or VIPT caches.  Note that this is unreliable since ARM926
- * and V6 CPUs satisfy the "(val & (15 << 25)) == (14 << 25)" test.
- * There's no way to tell from the CacheType register what type (!)
- * the cache is.
- */
-#define cache_is_vivt()                                                 \
-        ({                                                              \
-                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
-                (!__cacheid_present(__val)) || __cacheid_vivt(__val);   \
-        })
-                
-#define cache_is_vipt()                                                 \
-        ({                                                              \
-                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
-                __cacheid_present(__val) && __cacheid_vipt(__val);      \
-        })
-
-#define cache_is_vipt_nonaliasing()                                     \
-        ({                                                              \
-                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
-                __cacheid_present(__val) &&                             \
-                 __cacheid_vipt_nonaliasing(__val);                     \
-        })
-
-#define cache_is_vipt_aliasing()                                        \
-        ({                                                              \
-                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
-                __cacheid_present(__val) &&                             \
-                 __cacheid_vipt_aliasing(__val);                        \
-        })
-
-#define icache_is_vivt_asid_tagged()                                    \
-        ({                                                              \
-                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
-                __cacheid_present(__val) &&                             \
-                 __cacheid_vivt_asid_tagged_instr(__val);               \
-        })
-
-#endif
-
 #endif