Merge branch 'x86/irq' into x86/apic

Merge reason:
	Conflicts in arch/x86/kernel/apic/io_apic.c

Resolved Conflicts:
	arch/x86/kernel/apic/io_apic.c

Signed-off-by: H. Peter Anvin <hpa@zytor.com>

1 files changed, 17 insertions, 3 deletions

diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 730aefcfbee3..c77d2fa1f6e5 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -154,16 +154,16 @@
  *      Please note that the implementation of these, and the required
  *      effects are cache-type (VIVT/VIPT/PIPT) specific.
  *
- *      flush_cache_kern_all()
+ *      flush_kern_all()
  *
  *              Unconditionally clean and invalidate the entire cache.
  *
- *      flush_cache_user_mm(mm)
+ *      flush_user_all()
  *
  *              Clean and invalidate all user space cache entries
  *              before a change of page tables.
  *
- *      flush_cache_user_range(start, end, flags)
+ *      flush_user_range(start, end, flags)
  *
  *              Clean and invalidate a range of cache entries in the
  *              specified address space before a change of page tables.
@@ -179,6 +179,20 @@
  *              - start  - virtual start address
  *              - end    - virtual end address
  *
+ *      coherent_user_range(start, end)
+ *
+ *              Ensure coherency between the Icache and the Dcache in the
+ *              region described by start, end.  If you have non-snooping
+ *              Harvard caches, you need to implement this function.
+ *              - start  - virtual start address
+ *              - end    - virtual end address
+ *
+ *      flush_kern_dcache_area(kaddr, size)
+ *
+ *              Ensure that the data held in page is written back.
+ *              - kaddr  - page address
+ *              - size   - region size
+ *
  *      DMA Cache Coherency
  *      ===================
  *