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| author | Chris Metcalf <cmetcalf@tilera.com> | 2010-08-13 19:59:15 -0400 |
|---|---|---|
| committer | Chris Metcalf <cmetcalf@tilera.com> | 2010-08-13 19:59:15 -0400 |
| commit | 7d72e6fa56c4100b9669efe0044f77ed9eb785a1 (patch) | |
| tree | 5e90bf4969809a1ab20b97432b85be20ccfaa1f4 /arch/arm/include/asm/cache.h | |
| parent | ba00376b0b13f234d839541a7b36a5bf5c2a4036 (diff) | |
| parent | 2be1f3a73dd02e38e181cf5abacb3d45a6a2d6b8 (diff) | |
Merge branch 'master' into for-linus
Diffstat (limited to 'arch/arm/include/asm/cache.h')
| -rw-r--r-- | arch/arm/include/asm/cache.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index 66c160b8547f..9d6122096fbe 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h | |||
| @@ -14,7 +14,7 @@ | |||
| 14 | * cache before the transfer is done, causing old data to be seen by | 14 | * cache before the transfer is done, causing old data to be seen by |
| 15 | * the CPU. | 15 | * the CPU. |
| 16 | */ | 16 | */ |
| 17 | #define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES | 17 | #define ARCH_DMA_MINALIGN L1_CACHE_BYTES |
| 18 | 18 | ||
| 19 | /* | 19 | /* |
| 20 | * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers. | 20 | * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers. |