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authorChao Xie <xiechao.linux@gmail.com>2010-12-06 01:01:10 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-12-06 06:03:31 -0500
commit87507500b7fc3620e467abb617a3452f0cccc72d (patch)
tree6e59fe7fa70cdba79f300a62fc26acb48234bc32 /arch/arm/common
parenta5542a0f9aca5588a0afd0489c26d858405bfecb (diff)
ARM: 6524/1: GIC irq desciptor bug fix
gic_set_cpu will directly use irq_desc[]. If CONFIG_SPARSE_IRQ is enabled, there is no irq_desc[]. So we need use irq_to_desc(irq) to get the descriptor for irq. Signed-off-by: Chao Xie <chao.xie@marvell.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/common')
-rw-r--r--arch/arm/common/gic.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index fea1bd7249b6..e6388dcd8cfa 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -146,9 +146,15 @@ static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val)
146 unsigned int shift = (irq % 4) * 8; 146 unsigned int shift = (irq % 4) * 8;
147 unsigned int cpu = cpumask_first(mask_val); 147 unsigned int cpu = cpumask_first(mask_val);
148 u32 val; 148 u32 val;
149 struct irq_desc *desc;
149 150
150 spin_lock(&irq_controller_lock); 151 spin_lock(&irq_controller_lock);
151 irq_desc[irq].node = cpu; 152 desc = irq_to_desc(irq);
153 if (desc == NULL) {
154 spin_unlock(&irq_controller_lock);
155 return -EINVAL;
156 }
157 desc->node = cpu;
152 val = readl(reg) & ~(0xff << shift); 158 val = readl(reg) & ~(0xff << shift);
153 val |= 1 << (cpu + shift); 159 val |= 1 << (cpu + shift);
154 writel(val, reg); 160 writel(val, reg);