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authorRob Herring <rob.herring@calxeda.com>2012-10-27 18:25:26 -0400
committerRob Herring <rob.herring@calxeda.com>2013-01-12 11:52:14 -0500
commit44430ec068b207f985aa00b1d34bb5085dbc39d5 (patch)
tree6d2e69370398a9702128eb786c6bcf2c5eddf3a7 /arch/arm/common
parent48cf83dc12f2a5ef3ac4d74dc7b5e6403cb3cedb (diff)
irqchip: Move ARM VIC to drivers/irqchip
Now that we have drivers/irqchip, move VIC irqchip to drivers/irqchip. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/arm/common')
-rw-r--r--arch/arm/common/Kconfig15
-rw-r--r--arch/arm/common/Makefile1
-rw-r--r--arch/arm/common/vic.c484
3 files changed, 0 insertions, 500 deletions
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index 7bf52b2b7d33..9353184d730d 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -1,18 +1,3 @@
1config ARM_VIC
2 bool
3 select IRQ_DOMAIN
4 select MULTI_IRQ_HANDLER
5
6config ARM_VIC_NR
7 int
8 default 4 if ARCH_S5PV210
9 default 3 if ARCH_S5PC100
10 default 2
11 depends on ARM_VIC
12 help
13 The maximum number of VICs available in the system, for
14 power management.
15
16config ICST 1config ICST
17 bool 2 bool
18 3
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 4104b821f860..dc8dd0de5c0f 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -2,7 +2,6 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5obj-$(CONFIG_ARM_VIC) += vic.o
6obj-$(CONFIG_ICST) += icst.o 5obj-$(CONFIG_ICST) += icst.o
7obj-$(CONFIG_SA1111) += sa1111.o 6obj-$(CONFIG_SA1111) += sa1111.o
8obj-$(CONFIG_PCI_HOST_VIA82C505) += via82c505.o 7obj-$(CONFIG_PCI_HOST_VIA82C505) += via82c505.o
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
deleted file mode 100644
index 49af6187885f..000000000000
--- a/arch/arm/common/vic.c
+++ /dev/null
@@ -1,484 +0,0 @@
1/*
2 * linux/arch/arm/common/vic.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/export.h>
23#include <linux/init.h>
24#include <linux/list.h>
25#include <linux/io.h>
26#include <linux/irqdomain.h>
27#include <linux/of.h>
28#include <linux/of_address.h>
29#include <linux/of_irq.h>
30#include <linux/syscore_ops.h>
31#include <linux/device.h>
32#include <linux/amba/bus.h>
33
34#include <asm/exception.h>
35#include <asm/mach/irq.h>
36#include <asm/hardware/vic.h>
37
38#define VIC_IRQ_STATUS 0x00
39#define VIC_FIQ_STATUS 0x04
40#define VIC_INT_SELECT 0x0c /* 1 = FIQ, 0 = IRQ */
41#define VIC_INT_SOFT 0x18
42#define VIC_INT_SOFT_CLEAR 0x1c
43#define VIC_PROTECT 0x20
44#define VIC_PL190_VECT_ADDR 0x30 /* PL190 only */
45#define VIC_PL190_DEF_VECT_ADDR 0x34 /* PL190 only */
46
47#define VIC_VECT_ADDR0 0x100 /* 0 to 15 (0..31 PL192) */
48#define VIC_VECT_CNTL0 0x200 /* 0 to 15 (0..31 PL192) */
49#define VIC_ITCR 0x300 /* VIC test control register */
50
51#define VIC_VECT_CNTL_ENABLE (1 << 5)
52
53#define VIC_PL192_VECT_ADDR 0xF00
54
55/**
56 * struct vic_device - VIC PM device
57 * @irq: The IRQ number for the base of the VIC.
58 * @base: The register base for the VIC.
59 * @valid_sources: A bitmask of valid interrupts
60 * @resume_sources: A bitmask of interrupts for resume.
61 * @resume_irqs: The IRQs enabled for resume.
62 * @int_select: Save for VIC_INT_SELECT.
63 * @int_enable: Save for VIC_INT_ENABLE.
64 * @soft_int: Save for VIC_INT_SOFT.
65 * @protect: Save for VIC_PROTECT.
66 * @domain: The IRQ domain for the VIC.
67 */
68struct vic_device {
69 void __iomem *base;
70 int irq;
71 u32 valid_sources;
72 u32 resume_sources;
73 u32 resume_irqs;
74 u32 int_select;
75 u32 int_enable;
76 u32 soft_int;
77 u32 protect;
78 struct irq_domain *domain;
79};
80
81/* we cannot allocate memory when VICs are initially registered */
82static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
83
84static int vic_id;
85
86static void vic_handle_irq(struct pt_regs *regs);
87
88/**
89 * vic_init2 - common initialisation code
90 * @base: Base of the VIC.
91 *
92 * Common initialisation code for registration
93 * and resume.
94*/
95static void vic_init2(void __iomem *base)
96{
97 int i;
98
99 for (i = 0; i < 16; i++) {
100 void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
101 writel(VIC_VECT_CNTL_ENABLE | i, reg);
102 }
103
104 writel(32, base + VIC_PL190_DEF_VECT_ADDR);
105}
106
107#ifdef CONFIG_PM
108static void resume_one_vic(struct vic_device *vic)
109{
110 void __iomem *base = vic->base;
111
112 printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);
113
114 /* re-initialise static settings */
115 vic_init2(base);
116
117 writel(vic->int_select, base + VIC_INT_SELECT);
118 writel(vic->protect, base + VIC_PROTECT);
119
120 /* set the enabled ints and then clear the non-enabled */
121 writel(vic->int_enable, base + VIC_INT_ENABLE);
122 writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
123
124 /* and the same for the soft-int register */
125
126 writel(vic->soft_int, base + VIC_INT_SOFT);
127 writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
128}
129
130static void vic_resume(void)
131{
132 int id;
133
134 for (id = vic_id - 1; id >= 0; id--)
135 resume_one_vic(vic_devices + id);
136}
137
138static void suspend_one_vic(struct vic_device *vic)
139{
140 void __iomem *base = vic->base;
141
142 printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);
143
144 vic->int_select = readl(base + VIC_INT_SELECT);
145 vic->int_enable = readl(base + VIC_INT_ENABLE);
146 vic->soft_int = readl(base + VIC_INT_SOFT);
147 vic->protect = readl(base + VIC_PROTECT);
148
149 /* set the interrupts (if any) that are used for
150 * resuming the system */
151
152 writel(vic->resume_irqs, base + VIC_INT_ENABLE);
153 writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
154}
155
156static int vic_suspend(void)
157{
158 int id;
159
160 for (id = 0; id < vic_id; id++)
161 suspend_one_vic(vic_devices + id);
162
163 return 0;
164}
165
166struct syscore_ops vic_syscore_ops = {
167 .suspend = vic_suspend,
168 .resume = vic_resume,
169};
170
171/**
172 * vic_pm_init - initicall to register VIC pm
173 *
174 * This is called via late_initcall() to register
175 * the resources for the VICs due to the early
176 * nature of the VIC's registration.
177*/
178static int __init vic_pm_init(void)
179{
180 if (vic_id > 0)
181 register_syscore_ops(&vic_syscore_ops);
182
183 return 0;
184}
185late_initcall(vic_pm_init);
186#endif /* CONFIG_PM */
187
188static struct irq_chip vic_chip;
189
190static int vic_irqdomain_map(struct irq_domain *d, unsigned int irq,
191 irq_hw_number_t hwirq)
192{
193 struct vic_device *v = d->host_data;
194
195 /* Skip invalid IRQs, only register handlers for the real ones */
196 if (!(v->valid_sources & (1 << hwirq)))
197 return -ENOTSUPP;
198 irq_set_chip_and_handler(irq, &vic_chip, handle_level_irq);
199 irq_set_chip_data(irq, v->base);
200 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
201 return 0;
202}
203
204/*
205 * Handle each interrupt in a single VIC. Returns non-zero if we've
206 * handled at least one interrupt. This reads the status register
207 * before handling each interrupt, which is necessary given that
208 * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
209 */
210static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
211{
212 u32 stat, irq;
213 int handled = 0;
214
215 while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
216 irq = ffs(stat) - 1;
217 handle_IRQ(irq_find_mapping(vic->domain, irq), regs);
218 handled = 1;
219 }
220
221 return handled;
222}
223
224/*
225 * Keep iterating over all registered VIC's until there are no pending
226 * interrupts.
227 */
228static asmlinkage void __exception_irq_entry vic_handle_irq(struct pt_regs *regs)
229{
230 int i, handled;
231
232 do {
233 for (i = 0, handled = 0; i < vic_id; ++i)
234 handled |= handle_one_vic(&vic_devices[i], regs);
235 } while (handled);
236}
237
238static struct irq_domain_ops vic_irqdomain_ops = {
239 .map = vic_irqdomain_map,
240 .xlate = irq_domain_xlate_onetwocell,
241};
242
243/**
244 * vic_register() - Register a VIC.
245 * @base: The base address of the VIC.
246 * @irq: The base IRQ for the VIC.
247 * @valid_sources: bitmask of valid interrupts
248 * @resume_sources: bitmask of interrupts allowed for resume sources.
249 * @node: The device tree node associated with the VIC.
250 *
251 * Register the VIC with the system device tree so that it can be notified
252 * of suspend and resume requests and ensure that the correct actions are
253 * taken to re-instate the settings on resume.
254 *
255 * This also configures the IRQ domain for the VIC.
256 */
257static void __init vic_register(void __iomem *base, unsigned int irq,
258 u32 valid_sources, u32 resume_sources,
259 struct device_node *node)
260{
261 struct vic_device *v;
262 int i;
263
264 if (vic_id >= ARRAY_SIZE(vic_devices)) {
265 printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
266 return;
267 }
268
269 v = &vic_devices[vic_id];
270 v->base = base;
271 v->valid_sources = valid_sources;
272 v->resume_sources = resume_sources;
273 v->irq = irq;
274 set_handle_irq(vic_handle_irq);
275 vic_id++;
276 v->domain = irq_domain_add_simple(node, fls(valid_sources), irq,
277 &vic_irqdomain_ops, v);
278 /* create an IRQ mapping for each valid IRQ */
279 for (i = 0; i < fls(valid_sources); i++)
280 if (valid_sources & (1 << i))
281 irq_create_mapping(v->domain, i);
282}
283
284static void vic_ack_irq(struct irq_data *d)
285{
286 void __iomem *base = irq_data_get_irq_chip_data(d);
287 unsigned int irq = d->hwirq;
288 writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
289 /* moreover, clear the soft-triggered, in case it was the reason */
290 writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
291}
292
293static void vic_mask_irq(struct irq_data *d)
294{
295 void __iomem *base = irq_data_get_irq_chip_data(d);
296 unsigned int irq = d->hwirq;
297 writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
298}
299
300static void vic_unmask_irq(struct irq_data *d)
301{
302 void __iomem *base = irq_data_get_irq_chip_data(d);
303 unsigned int irq = d->hwirq;
304 writel(1 << irq, base + VIC_INT_ENABLE);
305}
306
307#if defined(CONFIG_PM)
308static struct vic_device *vic_from_irq(unsigned int irq)
309{
310 struct vic_device *v = vic_devices;
311 unsigned int base_irq = irq & ~31;
312 int id;
313
314 for (id = 0; id < vic_id; id++, v++) {
315 if (v->irq == base_irq)
316 return v;
317 }
318
319 return NULL;
320}
321
322static int vic_set_wake(struct irq_data *d, unsigned int on)
323{
324 struct vic_device *v = vic_from_irq(d->irq);
325 unsigned int off = d->hwirq;
326 u32 bit = 1 << off;
327
328 if (!v)
329 return -EINVAL;
330
331 if (!(bit & v->resume_sources))
332 return -EINVAL;
333
334 if (on)
335 v->resume_irqs |= bit;
336 else
337 v->resume_irqs &= ~bit;
338
339 return 0;
340}
341#else
342#define vic_set_wake NULL
343#endif /* CONFIG_PM */
344
345static struct irq_chip vic_chip = {
346 .name = "VIC",
347 .irq_ack = vic_ack_irq,
348 .irq_mask = vic_mask_irq,
349 .irq_unmask = vic_unmask_irq,
350 .irq_set_wake = vic_set_wake,
351};
352
353static void __init vic_disable(void __iomem *base)
354{
355 writel(0, base + VIC_INT_SELECT);
356 writel(0, base + VIC_INT_ENABLE);
357 writel(~0, base + VIC_INT_ENABLE_CLEAR);
358 writel(0, base + VIC_ITCR);
359 writel(~0, base + VIC_INT_SOFT_CLEAR);
360}
361
362static void __init vic_clear_interrupts(void __iomem *base)
363{
364 unsigned int i;
365
366 writel(0, base + VIC_PL190_VECT_ADDR);
367 for (i = 0; i < 19; i++) {
368 unsigned int value;
369
370 value = readl(base + VIC_PL190_VECT_ADDR);
371 writel(value, base + VIC_PL190_VECT_ADDR);
372 }
373}
374
375/*
376 * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
377 * The original cell has 32 interrupts, while the modified one has 64,
378 * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
379 * the probe function is called twice, with base set to offset 000
380 * and 020 within the page. We call this "second block".
381 */
382static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
383 u32 vic_sources, struct device_node *node)
384{
385 unsigned int i;
386 int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
387
388 /* Disable all interrupts initially. */
389 vic_disable(base);
390
391 /*
392 * Make sure we clear all existing interrupts. The vector registers
393 * in this cell are after the second block of general registers,
394 * so we can address them using standard offsets, but only from
395 * the second base address, which is 0x20 in the page
396 */
397 if (vic_2nd_block) {
398 vic_clear_interrupts(base);
399
400 /* ST has 16 vectors as well, but we don't enable them by now */
401 for (i = 0; i < 16; i++) {
402 void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
403 writel(0, reg);
404 }
405
406 writel(32, base + VIC_PL190_DEF_VECT_ADDR);
407 }
408
409 vic_register(base, irq_start, vic_sources, 0, node);
410}
411
412void __init __vic_init(void __iomem *base, int irq_start,
413 u32 vic_sources, u32 resume_sources,
414 struct device_node *node)
415{
416 unsigned int i;
417 u32 cellid = 0;
418 enum amba_vendor vendor;
419
420 /* Identify which VIC cell this one is, by reading the ID */
421 for (i = 0; i < 4; i++) {
422 void __iomem *addr;
423 addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
424 cellid |= (readl(addr) & 0xff) << (8 * i);
425 }
426 vendor = (cellid >> 12) & 0xff;
427 printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n",
428 base, cellid, vendor);
429
430 switch(vendor) {
431 case AMBA_VENDOR_ST:
432 vic_init_st(base, irq_start, vic_sources, node);
433 return;
434 default:
435 printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
436 /* fall through */
437 case AMBA_VENDOR_ARM:
438 break;
439 }
440
441 /* Disable all interrupts initially. */
442 vic_disable(base);
443
444 /* Make sure we clear all existing interrupts */
445 vic_clear_interrupts(base);
446
447 vic_init2(base);
448
449 vic_register(base, irq_start, vic_sources, resume_sources, node);
450}
451
452/**
453 * vic_init() - initialise a vectored interrupt controller
454 * @base: iomem base address
455 * @irq_start: starting interrupt number, must be muliple of 32
456 * @vic_sources: bitmask of interrupt sources to allow
457 * @resume_sources: bitmask of interrupt sources to allow for resume
458 */
459void __init vic_init(void __iomem *base, unsigned int irq_start,
460 u32 vic_sources, u32 resume_sources)
461{
462 __vic_init(base, irq_start, vic_sources, resume_sources, NULL);
463}
464
465#ifdef CONFIG_OF
466int __init vic_of_init(struct device_node *node, struct device_node *parent)
467{
468 void __iomem *regs;
469
470 if (WARN(parent, "non-root VICs are not supported"))
471 return -EINVAL;
472
473 regs = of_iomap(node, 0);
474 if (WARN_ON(!regs))
475 return -EIO;
476
477 /*
478 * Passing 0 as first IRQ makes the simple domain allocate descriptors
479 */
480 __vic_init(regs, 0, ~0, ~0, node);
481
482 return 0;
483}
484#endif /* CONFIG OF */
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