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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2006-03-15 10:44:29 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-03-21 17:05:52 -0500
commit824b5b5e59472c89bc508afa5c453547c91ed53b (patch)
treea3bdb4feb4bad9ba4fea55c6801d70bfe50e3926 /arch/arm/common/vic.c
parent548153663bbf33ca7c244a6bbddd82c26a17c331 (diff)
[ARM] Adapt vic.c to allow for multiple VICs in a system.
Some SoCs have multiple VIC devices. Adapt the generic vic code to allow multiple implementations to be handled. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/common/vic.c')
-rw-r--r--arch/arm/common/vic.c49
1 files changed, 27 insertions, 22 deletions
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index a45ed1687a59..a19bc4a6196d 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -22,22 +22,21 @@
22#include <linux/list.h> 22#include <linux/list.h>
23 23
24#include <asm/io.h> 24#include <asm/io.h>
25#include <asm/irq.h>
26#include <asm/mach/irq.h> 25#include <asm/mach/irq.h>
27#include <asm/hardware/vic.h> 26#include <asm/hardware/vic.h>
28 27
29static void __iomem *vic_base;
30
31static void vic_mask_irq(unsigned int irq) 28static void vic_mask_irq(unsigned int irq)
32{ 29{
33 irq -= IRQ_VIC_START; 30 void __iomem *base = get_irq_chipdata(irq);
34 writel(1 << irq, vic_base + VIC_INT_ENABLE_CLEAR); 31 irq &= 31;
32 writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
35} 33}
36 34
37static void vic_unmask_irq(unsigned int irq) 35static void vic_unmask_irq(unsigned int irq)
38{ 36{
39 irq -= IRQ_VIC_START; 37 void __iomem *base = get_irq_chipdata(irq);
40 writel(1 << irq, vic_base + VIC_INT_ENABLE); 38 irq &= 31;
39 writel(1 << irq, base + VIC_INT_ENABLE);
41} 40}
42 41
43static struct irqchip vic_chip = { 42static struct irqchip vic_chip = {
@@ -46,43 +45,49 @@ static struct irqchip vic_chip = {
46 .unmask = vic_unmask_irq, 45 .unmask = vic_unmask_irq,
47}; 46};
48 47
49void __init vic_init(void __iomem *base, u32 vic_sources) 48/**
49 * vic_init - initialise a vectored interrupt controller
50 * @base: iomem base address
51 * @irq_start: starting interrupt number, must be muliple of 32
52 * @vic_sources: bitmask of interrupt sources to allow
53 */
54void __init vic_init(void __iomem *base, unsigned int irq_start,
55 u32 vic_sources)
50{ 56{
51 unsigned int i; 57 unsigned int i;
52 58
53 vic_base = base;
54
55 /* Disable all interrupts initially. */ 59 /* Disable all interrupts initially. */
56 60
57 writel(0, vic_base + VIC_INT_SELECT); 61 writel(0, base + VIC_INT_SELECT);
58 writel(0, vic_base + VIC_INT_ENABLE); 62 writel(0, base + VIC_INT_ENABLE);
59 writel(~0, vic_base + VIC_INT_ENABLE_CLEAR); 63 writel(~0, base + VIC_INT_ENABLE_CLEAR);
60 writel(0, vic_base + VIC_IRQ_STATUS); 64 writel(0, base + VIC_IRQ_STATUS);
61 writel(0, vic_base + VIC_ITCR); 65 writel(0, base + VIC_ITCR);
62 writel(~0, vic_base + VIC_INT_SOFT_CLEAR); 66 writel(~0, base + VIC_INT_SOFT_CLEAR);
63 67
64 /* 68 /*
65 * Make sure we clear all existing interrupts 69 * Make sure we clear all existing interrupts
66 */ 70 */
67 writel(0, vic_base + VIC_VECT_ADDR); 71 writel(0, base + VIC_VECT_ADDR);
68 for (i = 0; i < 19; i++) { 72 for (i = 0; i < 19; i++) {
69 unsigned int value; 73 unsigned int value;
70 74
71 value = readl(vic_base + VIC_VECT_ADDR); 75 value = readl(base + VIC_VECT_ADDR);
72 writel(value, vic_base + VIC_VECT_ADDR); 76 writel(value, base + VIC_VECT_ADDR);
73 } 77 }
74 78
75 for (i = 0; i < 16; i++) { 79 for (i = 0; i < 16; i++) {
76 void __iomem *reg = vic_base + VIC_VECT_CNTL0 + (i * 4); 80 void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
77 writel(VIC_VECT_CNTL_ENABLE | i, reg); 81 writel(VIC_VECT_CNTL_ENABLE | i, reg);
78 } 82 }
79 83
80 writel(32, vic_base + VIC_DEF_VECT_ADDR); 84 writel(32, base + VIC_DEF_VECT_ADDR);
81 85
82 for (i = 0; i < 32; i++) { 86 for (i = 0; i < 32; i++) {
83 unsigned int irq = IRQ_VIC_START + i; 87 unsigned int irq = irq_start + i;
84 88
85 set_irq_chip(irq, &vic_chip); 89 set_irq_chip(irq, &vic_chip);
90 set_irq_chipdata(irq, base);
86 91
87 if (vic_sources & (1 << i)) { 92 if (vic_sources & (1 << i)) {
88 set_irq_handler(irq, do_level_IRQ); 93 set_irq_handler(irq, do_level_IRQ);