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| author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-03-22 20:32:09 -0500 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-03-22 20:32:09 -0500 |
| commit | 591eb85ecd7e6eb8596c6129ae074e16636b99f4 (patch) | |
| tree | 535fb7e9bc29113ff62fd70b0dcd8ad197ab51e2 /arch/arm/common/vic.c | |
| parent | 4658f79bec0b51222e769e328c2923f39f3bda77 (diff) | |
| parent | 3a2916aa289504d694072a98876d23ca31d6401e (diff) | |
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: (45 commits)
[ARM] 3389/1: typo and grammar fix
[ARM] 3386/1: AT91RM9200 Clock update
[ARM] 3384/1: AT91RM9200: Timer
[ARM] 3382/1: ixp2000: unify defconfigs
[ARM] 3381/1: ixp2000: fix slowport write timing control register fields
[ARM] 3380/1: ixp2000: simplify ixdp2x00_master_npu() check
[ARM] 3379/1: ixp2000: use generic 8250 debug macros
[ARM] 3378/1: ixp2000: fix gpio interrupt handling
[ARM] Quieten spurious IRQ detection
[ARM] Use kcalloc to allocate counter_config array rather than kmalloc
[ARM] Oprofile: dynamically allocate counter_config
[ARM] Oprofile: Convert semaphore to mutex
[ARM] 3376/2: S3C2410 - update defconfig
[ARM] 3375/1: S3C2440 - fix osiris machine build
[ARM] 3374/1: ep93xx: gpio interrupt support
[ARM] 3361/1: S3C24XX - add USB bus clock source
[ARM] 3360/1: S3C2440 - add set rate methods and camera clock
[ARM] 3359/1: S3C24XX - add support for clk_set_rate
[ARM] Convert kmalloc+memset to kzalloc
[ARM] 3373/1: move uengine loader to arch/arm/common
...
Diffstat (limited to 'arch/arm/common/vic.c')
| -rw-r--r-- | arch/arm/common/vic.c | 49 |
1 files changed, 27 insertions, 22 deletions
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c index a45ed1687a59..a19bc4a6196d 100644 --- a/arch/arm/common/vic.c +++ b/arch/arm/common/vic.c | |||
| @@ -22,22 +22,21 @@ | |||
| 22 | #include <linux/list.h> | 22 | #include <linux/list.h> |
| 23 | 23 | ||
| 24 | #include <asm/io.h> | 24 | #include <asm/io.h> |
| 25 | #include <asm/irq.h> | ||
| 26 | #include <asm/mach/irq.h> | 25 | #include <asm/mach/irq.h> |
| 27 | #include <asm/hardware/vic.h> | 26 | #include <asm/hardware/vic.h> |
| 28 | 27 | ||
| 29 | static void __iomem *vic_base; | ||
| 30 | |||
| 31 | static void vic_mask_irq(unsigned int irq) | 28 | static void vic_mask_irq(unsigned int irq) |
| 32 | { | 29 | { |
| 33 | irq -= IRQ_VIC_START; | 30 | void __iomem *base = get_irq_chipdata(irq); |
| 34 | writel(1 << irq, vic_base + VIC_INT_ENABLE_CLEAR); | 31 | irq &= 31; |
| 32 | writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); | ||
| 35 | } | 33 | } |
| 36 | 34 | ||
| 37 | static void vic_unmask_irq(unsigned int irq) | 35 | static void vic_unmask_irq(unsigned int irq) |
| 38 | { | 36 | { |
| 39 | irq -= IRQ_VIC_START; | 37 | void __iomem *base = get_irq_chipdata(irq); |
| 40 | writel(1 << irq, vic_base + VIC_INT_ENABLE); | 38 | irq &= 31; |
| 39 | writel(1 << irq, base + VIC_INT_ENABLE); | ||
| 41 | } | 40 | } |
| 42 | 41 | ||
| 43 | static struct irqchip vic_chip = { | 42 | static struct irqchip vic_chip = { |
| @@ -46,43 +45,49 @@ static struct irqchip vic_chip = { | |||
| 46 | .unmask = vic_unmask_irq, | 45 | .unmask = vic_unmask_irq, |
| 47 | }; | 46 | }; |
| 48 | 47 | ||
| 49 | void __init vic_init(void __iomem *base, u32 vic_sources) | 48 | /** |
| 49 | * vic_init - initialise a vectored interrupt controller | ||
| 50 | * @base: iomem base address | ||
| 51 | * @irq_start: starting interrupt number, must be muliple of 32 | ||
| 52 | * @vic_sources: bitmask of interrupt sources to allow | ||
| 53 | */ | ||
| 54 | void __init vic_init(void __iomem *base, unsigned int irq_start, | ||
| 55 | u32 vic_sources) | ||
| 50 | { | 56 | { |
| 51 | unsigned int i; | 57 | unsigned int i; |
| 52 | 58 | ||
| 53 | vic_base = base; | ||
| 54 | |||
| 55 | /* Disable all interrupts initially. */ | 59 | /* Disable all interrupts initially. */ |
| 56 | 60 | ||
| 57 | writel(0, vic_base + VIC_INT_SELECT); | 61 | writel(0, base + VIC_INT_SELECT); |
| 58 | writel(0, vic_base + VIC_INT_ENABLE); | 62 | writel(0, base + VIC_INT_ENABLE); |
| 59 | writel(~0, vic_base + VIC_INT_ENABLE_CLEAR); | 63 | writel(~0, base + VIC_INT_ENABLE_CLEAR); |
| 60 | writel(0, vic_base + VIC_IRQ_STATUS); | 64 | writel(0, base + VIC_IRQ_STATUS); |
| 61 | writel(0, vic_base + VIC_ITCR); | 65 | writel(0, base + VIC_ITCR); |
| 62 | writel(~0, vic_base + VIC_INT_SOFT_CLEAR); | 66 | writel(~0, base + VIC_INT_SOFT_CLEAR); |
| 63 | 67 | ||
| 64 | /* | 68 | /* |
| 65 | * Make sure we clear all existing interrupts | 69 | * Make sure we clear all existing interrupts |
| 66 | */ | 70 | */ |
| 67 | writel(0, vic_base + VIC_VECT_ADDR); | 71 | writel(0, base + VIC_VECT_ADDR); |
| 68 | for (i = 0; i < 19; i++) { | 72 | for (i = 0; i < 19; i++) { |
| 69 | unsigned int value; | 73 | unsigned int value; |
| 70 | 74 | ||
| 71 | value = readl(vic_base + VIC_VECT_ADDR); | 75 | value = readl(base + VIC_VECT_ADDR); |
| 72 | writel(value, vic_base + VIC_VECT_ADDR); | 76 | writel(value, base + VIC_VECT_ADDR); |
| 73 | } | 77 | } |
| 74 | 78 | ||
| 75 | for (i = 0; i < 16; i++) { | 79 | for (i = 0; i < 16; i++) { |
| 76 | void __iomem *reg = vic_base + VIC_VECT_CNTL0 + (i * 4); | 80 | void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); |
| 77 | writel(VIC_VECT_CNTL_ENABLE | i, reg); | 81 | writel(VIC_VECT_CNTL_ENABLE | i, reg); |
| 78 | } | 82 | } |
| 79 | 83 | ||
| 80 | writel(32, vic_base + VIC_DEF_VECT_ADDR); | 84 | writel(32, base + VIC_DEF_VECT_ADDR); |
| 81 | 85 | ||
| 82 | for (i = 0; i < 32; i++) { | 86 | for (i = 0; i < 32; i++) { |
| 83 | unsigned int irq = IRQ_VIC_START + i; | 87 | unsigned int irq = irq_start + i; |
| 84 | 88 | ||
| 85 | set_irq_chip(irq, &vic_chip); | 89 | set_irq_chip(irq, &vic_chip); |
| 90 | set_irq_chipdata(irq, base); | ||
| 86 | 91 | ||
| 87 | if (vic_sources & (1 << i)) { | 92 | if (vic_sources & (1 << i)) { |
| 88 | set_irq_handler(irq, do_level_IRQ); | 93 | set_irq_handler(irq, do_level_IRQ); |
