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authorLinus Torvalds <torvalds@linux-foundation.org>2009-06-22 17:56:13 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-06-22 17:56:13 -0400
commit9e268beb92ee3a853b3946e84b10358207e2085f (patch)
treedec36344c8b16d53e56763aa174dd7ea806b653f /arch/arm/common/gic.c
parent2e8b5a09ebf1f98f02c1988a48415e89d4c25168 (diff)
parent9ccdac3662dbf3c75e8f8851a214bdf7d365a4bd (diff)
Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (49 commits) [ARM] idle: clean up pm_idle calling, obey hlt_counter [ARM] S3C: Fix gpio-config off-by-one bug [ARM] S3C64XX: add to_irq() support for EINT() GPIO [ARM] S3C64XX: clock.c: fix typo in usb-host clock ctrlbit [ARM] S3C64XX: fix HCLK gate defines [ARM] Update mach-types [ARM] wire up rt_tgsigqueueinfo and perf_counter_open OMAP2 clock/powerdomain: off by 1 error in loop timeout comparisons OMAP3 SDRC: set FIXEDDELAY when disabling SDRC DLL OMAP3: Add support for DPLL3 divisor values higher than 2 OMAP3 SRAM: convert SRAM code to use macros rather than magic numbers OMAP3 SRAM: add more comments on the SRAM code OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change OMAP3 clock: add a short delay when lowering CORE clk rate OMAP3 clock: initialize SDRC timings at kernel start OMAP3 clock: remove wait for DPLL3 M2 clock to stabilize [ARM] Add old Feroceon support to compressed/head.S [ARM] 5559/1: Limit the stack unwinding caused by a kthread exit [ARM] 5558/1: Add extra checks to ARM unwinder to avoid tracing corrupt stacks [ARM] 5557/1: Discard some ARM.ex*.*exit.text sections when !HOTPLUG or !HOTPLUG_CPU ...
Diffstat (limited to 'arch/arm/common/gic.c')
-rw-r--r--arch/arm/common/gic.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 664c7b8b1ba8..337741f734ac 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -117,7 +117,7 @@ static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val)
117 u32 val; 117 u32 val;
118 118
119 spin_lock(&irq_controller_lock); 119 spin_lock(&irq_controller_lock);
120 irq_desc[irq].cpu = cpu; 120 irq_desc[irq].node = cpu;
121 val = readl(reg) & ~(0xff << shift); 121 val = readl(reg) & ~(0xff << shift);
122 val |= 1 << (cpu + shift); 122 val |= 1 << (cpu + shift);
123 writel(val, reg); 123 writel(val, reg);