diff options
| author | Dan Williams <dan.j.williams@intel.com> | 2009-09-08 20:55:21 -0400 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2009-09-08 20:55:21 -0400 |
| commit | bbb20089a3275a19e475dbc21320c3742e3ca423 (patch) | |
| tree | 216fdc1cbef450ca688135c5b8969169482d9a48 /arch/arm/common/gic.c | |
| parent | 3e48e656903e9fd8bc805c6a2c4264d7808d315b (diff) | |
| parent | 657a77fa7284d8ae28dfa48f1dc5d919bf5b2843 (diff) | |
Merge branch 'dmaengine' into async-tx-next
Conflicts:
crypto/async_tx/async_xor.c
drivers/dma/ioat/dma_v2.h
drivers/dma/ioat/pci.c
drivers/md/raid5.c
Diffstat (limited to 'arch/arm/common/gic.c')
| -rw-r--r-- | arch/arm/common/gic.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index 3e1714c6523f..337741f734ac 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c | |||
| @@ -109,7 +109,7 @@ static void gic_unmask_irq(unsigned int irq) | |||
| 109 | } | 109 | } |
| 110 | 110 | ||
| 111 | #ifdef CONFIG_SMP | 111 | #ifdef CONFIG_SMP |
| 112 | static void gic_set_cpu(unsigned int irq, const struct cpumask *mask_val) | 112 | static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val) |
| 113 | { | 113 | { |
| 114 | void __iomem *reg = gic_dist_base(irq) + GIC_DIST_TARGET + (gic_irq(irq) & ~3); | 114 | void __iomem *reg = gic_dist_base(irq) + GIC_DIST_TARGET + (gic_irq(irq) & ~3); |
| 115 | unsigned int shift = (irq % 4) * 8; | 115 | unsigned int shift = (irq % 4) * 8; |
| @@ -117,11 +117,13 @@ static void gic_set_cpu(unsigned int irq, const struct cpumask *mask_val) | |||
| 117 | u32 val; | 117 | u32 val; |
| 118 | 118 | ||
| 119 | spin_lock(&irq_controller_lock); | 119 | spin_lock(&irq_controller_lock); |
| 120 | irq_desc[irq].cpu = cpu; | 120 | irq_desc[irq].node = cpu; |
| 121 | val = readl(reg) & ~(0xff << shift); | 121 | val = readl(reg) & ~(0xff << shift); |
| 122 | val |= 1 << (cpu + shift); | 122 | val |= 1 << (cpu + shift); |
| 123 | writel(val, reg); | 123 | writel(val, reg); |
| 124 | spin_unlock(&irq_controller_lock); | 124 | spin_unlock(&irq_controller_lock); |
| 125 | |||
| 126 | return 0; | ||
| 125 | } | 127 | } |
| 126 | #endif | 128 | #endif |
| 127 | 129 | ||
