diff options
| author | Michal Simek <michal.simek@xilinx.com> | 2014-09-24 09:16:01 -0400 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2014-10-20 09:19:10 -0400 |
| commit | 8abef06b63e639b910d202319be9e8151ac3a1ed (patch) | |
| tree | 52faa95cc47cb0f4dc525f279614e01d78efe44a /arch/arm/boot | |
| parent | e8b397754a712f1b3c3fbf448ad836034ecc6643 (diff) | |
ARM: zynq: DT: Add missing address for L2 pl310
By in sync with others node and add also baseaddr
to the node name.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/zynq-7000.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 1836a60444fa..772381fe07bb 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi | |||
| @@ -136,7 +136,7 @@ | |||
| 136 | <0xF8F00100 0x100>; | 136 | <0xF8F00100 0x100>; |
| 137 | }; | 137 | }; |
| 138 | 138 | ||
| 139 | L2: cache-controller { | 139 | L2: cache-controller@f8f02000 { |
| 140 | compatible = "arm,pl310-cache"; | 140 | compatible = "arm,pl310-cache"; |
| 141 | reg = <0xF8F02000 0x1000>; | 141 | reg = <0xF8F02000 0x1000>; |
| 142 | arm,data-latency = <3 2 2>; | 142 | arm,data-latency = <3 2 2>; |