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authorCatalin Marinas <catalin.marinas@arm.com>2006-06-18 11:21:50 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-06-18 11:21:50 -0400
commit45a7b9cf8e0634fa546e9e7ad29af990ab4afcf2 (patch)
tree2a9910617eeebe7f70b4406fe7843908b2a0359e /arch/arm/boot
parent5247593c9634309d1b9f7b549495b8e5ad521688 (diff)
[ARM] 3548/1: Fix the ARMv6 CPU id in compressed/head.S
Patch from Catalin Marinas This code was still using the old format for the ARMv6 CPU id and it wasn't flushing the caches on the MPCore CPU (and other ARM1176 cores). The patch changes the mask bits to cope with the new id format. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/compressed/head.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index b56f5e691d65..23016f6aa645 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -605,8 +605,8 @@ proc_types:
605 b __armv4_mmu_cache_off 605 b __armv4_mmu_cache_off
606 b __armv4_mmu_cache_flush 606 b __armv4_mmu_cache_flush
607 607
608 .word 0x00070000 @ ARMv6 608 .word 0x0007b000 @ ARMv6
609 .word 0x000f0000 609 .word 0x0007f000
610 b __armv4_mmu_cache_on 610 b __armv4_mmu_cache_on
611 b __armv4_mmu_cache_off 611 b __armv4_mmu_cache_off
612 b __armv6_mmu_cache_flush 612 b __armv6_mmu_cache_flush