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author | Arnd Bergmann <arnd@arndb.de> | 2011-10-20 12:15:30 -0400 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2011-10-20 12:15:30 -0400 |
commit | 107532920226a37e595697959b2a6a823cfa2497 (patch) | |
tree | 7d35c84ed324e6cabeed29282f1fc97994fd204b /arch/arm/boot | |
parent | 29ea35969b92a4be122a58c4aceea8c5e2c388d9 (diff) | |
parent | ecb7b0e33e048e63d1169e6fee277430c70ddf0b (diff) |
Merge branch 'tegra/devel' into next/devel
Diffstat (limited to 'arch/arm/boot')
-rw-r--r-- | arch/arm/boot/dts/tegra-ventana.dts | 32 | ||||
-rw-r--r-- | arch/arm/boot/dts/tegra20.dtsi | 8 |
2 files changed, 40 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts new file mode 100644 index 000000000000..9b29a623aaf1 --- /dev/null +++ b/arch/arm/boot/dts/tegra-ventana.dts | |||
@@ -0,0 +1,32 @@ | |||
1 | /dts-v1/; | ||
2 | |||
3 | /memreserve/ 0x1c000000 0x04000000; | ||
4 | /include/ "tegra20.dtsi" | ||
5 | |||
6 | / { | ||
7 | model = "NVIDIA Tegra2 Ventana evaluation board"; | ||
8 | compatible = "nvidia,ventana", "nvidia,tegra20"; | ||
9 | |||
10 | chosen { | ||
11 | bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/ram rdinit=/sbin/init"; | ||
12 | }; | ||
13 | |||
14 | memory { | ||
15 | reg = < 0x00000000 0x40000000 >; | ||
16 | }; | ||
17 | |||
18 | serial@70006300 { | ||
19 | clock-frequency = < 216000000 >; | ||
20 | }; | ||
21 | |||
22 | sdhci@c8000400 { | ||
23 | cd-gpios = <&gpio 69 0>; /* gpio PI5 */ | ||
24 | wp-gpios = <&gpio 57 0>; /* gpio PH1 */ | ||
25 | power-gpios = <&gpio 155 0>; /* gpio PT3 */ | ||
26 | }; | ||
27 | |||
28 | sdhci@c8000600 { | ||
29 | power-gpios = <&gpio 70 0>; /* gpio PI6 */ | ||
30 | support-8bit; | ||
31 | }; | ||
32 | }; | ||
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 5727595cde61..65d7e6a333eb 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi | |||
@@ -77,6 +77,14 @@ | |||
77 | gpio-controller; | 77 | gpio-controller; |
78 | }; | 78 | }; |
79 | 79 | ||
80 | pinmux: pinmux@70000000 { | ||
81 | compatible = "nvidia,tegra20-pinmux"; | ||
82 | reg = < 0x70000014 0x10 /* Tri-state registers */ | ||
83 | 0x70000080 0x20 /* Mux registers */ | ||
84 | 0x700000a0 0x14 /* Pull-up/down registers */ | ||
85 | 0x70000868 0xa8 >; /* Pad control registers */ | ||
86 | }; | ||
87 | |||
80 | serial@70006000 { | 88 | serial@70006000 { |
81 | compatible = "nvidia,tegra20-uart"; | 89 | compatible = "nvidia,tegra20-uart"; |
82 | reg = <0x70006000 0x40>; | 90 | reg = <0x70006000 0x40>; |