diff options
author | Catalin Marinas <catalin.marinas@arm.com> | 2008-11-06 08:23:07 -0500 |
---|---|---|
committer | Catalin Marinas <catalin.marinas@arm.com> | 2008-11-06 08:23:07 -0500 |
commit | c30c2f99e10b6a810dae9a25b35c6d48796d8ffb (patch) | |
tree | ba62c6796e789fc5dfcb16ec8cddb2f1c89203b8 /arch/arm/boot | |
parent | 2bedbdf4148ebbe48c7a89449ab52e475a788f42 (diff) |
ARMv7: Add extra barriers for flush_cache_all compressed/head.S
The flush_cache_all function on ARMv7 is implemented as a series of
cache operations by set/way. These are not guaranteed to be ordered with
previous memory accesses, requiring a DMB. This patch also adds barriers
for the TLB operations in compressed/head.S
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r-- | arch/arm/boot/compressed/head.S | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 84a1e0496a3c..7b1f31295a0a 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S | |||
@@ -717,6 +717,9 @@ __armv7_mmu_cache_off: | |||
717 | bl __armv7_mmu_cache_flush | 717 | bl __armv7_mmu_cache_flush |
718 | mov r0, #0 | 718 | mov r0, #0 |
719 | mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB | 719 | mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB |
720 | mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC | ||
721 | mcr p15, 0, r0, c7, c10, 4 @ DSB | ||
722 | mcr p15, 0, r0, c7, c5, 4 @ ISB | ||
720 | mov pc, r12 | 723 | mov pc, r12 |
721 | 724 | ||
722 | __arm6_mmu_cache_off: | 725 | __arm6_mmu_cache_off: |
@@ -778,12 +781,13 @@ __armv6_mmu_cache_flush: | |||
778 | __armv7_mmu_cache_flush: | 781 | __armv7_mmu_cache_flush: |
779 | mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1 | 782 | mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1 |
780 | tst r10, #0xf << 16 @ hierarchical cache (ARMv7) | 783 | tst r10, #0xf << 16 @ hierarchical cache (ARMv7) |
781 | beq hierarchical | ||
782 | mov r10, #0 | 784 | mov r10, #0 |
785 | beq hierarchical | ||
783 | mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D | 786 | mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D |
784 | b iflush | 787 | b iflush |
785 | hierarchical: | 788 | hierarchical: |
786 | stmfd sp!, {r0-r5, r7, r9-r11} | 789 | mcr p15, 0, r10, c7, c10, 5 @ DMB |
790 | stmfd sp!, {r0-r5, r7, r9, r11} | ||
787 | mrc p15, 1, r0, c0, c0, 1 @ read clidr | 791 | mrc p15, 1, r0, c0, c0, 1 @ read clidr |
788 | ands r3, r0, #0x7000000 @ extract loc from clidr | 792 | ands r3, r0, #0x7000000 @ extract loc from clidr |
789 | mov r3, r3, lsr #23 @ left align loc bit field | 793 | mov r3, r3, lsr #23 @ left align loc bit field |
@@ -820,12 +824,14 @@ skip: | |||
820 | cmp r3, r10 | 824 | cmp r3, r10 |
821 | bgt loop1 | 825 | bgt loop1 |
822 | finished: | 826 | finished: |
827 | ldmfd sp!, {r0-r5, r7, r9, r11} | ||
823 | mov r10, #0 @ swith back to cache level 0 | 828 | mov r10, #0 @ swith back to cache level 0 |
824 | mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr | 829 | mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr |
825 | ldmfd sp!, {r0-r5, r7, r9-r11} | ||
826 | iflush: | 830 | iflush: |
831 | mcr p15, 0, r10, c7, c10, 4 @ DSB | ||
827 | mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB | 832 | mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB |
828 | mcr p15, 0, r10, c7, c10, 4 @ drain WB | 833 | mcr p15, 0, r10, c7, c10, 4 @ DSB |
834 | mcr p15, 0, r10, c7, c5, 4 @ ISB | ||
829 | mov pc, lr | 835 | mov pc, lr |
830 | 836 | ||
831 | __armv5tej_mmu_cache_flush: | 837 | __armv5tej_mmu_cache_flush: |