Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into rmobile-latest

9 files changed, 964 insertions, 0 deletions

diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index 9128fddf1109..a1edfd5a129a 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -59,6 +59,12 @@ $(obj)/zImage:	$(obj)/compressed/vmlinux FORCE
 
 endif
 
+# Rule to build device tree blobs
+$(obj)/%.dtb: $(src)/dts/%.dts
+        $(call cmd,dtc)
+
+$(obj)/dtbs: $(addprefix $(obj)/, $(dtb-y))
+
 quiet_cmd_uimage = UIMAGE  $@
       cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A arm -O linux -T kernel \
                    -C none -a $(LOADADDR) -e $(STARTADDR) \
diff --git a/arch/arm/boot/dts/prima2-cb.dts b/arch/arm/boot/dts/prima2-cb.dts
new file mode 100644
index 000000000000..6fecc88065b2
--- /dev/null
+++ b/arch/arm/boot/dts/prima2-cb.dts
@@ -0,0 +1,416 @@
+/dts-v1/;
+/ {
+        model = "SiRF Prima2 eVB";
+        compatible = "sirf,prima2-cb", "sirf,prima2";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        interrupt-parent = <&intc>;
+
+        memory {
+                reg = <0x00000000 0x20000000>;
+        };
+
+        chosen {
+                bootargs = "mem=512M real_root=/dev/mmcblk0p2 console=ttyS0 panel=1 bootsplash=true bpp=16 androidboot.console=ttyS1";
+                linux,stdout-path = &uart1;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        reg = <0x0>;
+                        d-cache-line-size = <32>;
+                        i-cache-line-size = <32>;
+                        d-cache-size = <32768>;
+                        i-cache-size = <32768>;
+                        /* from bootloader */
+                        timebase-frequency = <0>;
+                        bus-frequency = <0>;
+                        clock-frequency = <0>;
+                };
+        };
+
+        axi {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0x40000000 0x40000000 0x80000000>;
+
+                l2-cache-controller@80040000 {
+                        compatible = "arm,pl310-cache";
+                        reg = <0x80040000 0x1000>;
+                        interrupts = <59>;
+                };
+
+                intc: interrupt-controller@80020000 {
+                        #interrupt-cells = <1>;
+                        interrupt-controller;
+                        compatible = "sirf,prima2-intc";
+                        reg = <0x80020000 0x1000>;
+                };
+
+                sys-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x88000000 0x88000000 0x40000>;
+
+                        clock-controller@88000000 {
+                                compatible = "sirf,prima2-clkc";
+                                reg = <0x88000000 0x1000>;
+                                interrupts = <3>;
+                        };
+
+                        reset-controller@88010000 {
+                                compatible = "sirf,prima2-rstc";
+                                reg = <0x88010000 0x1000>;
+                        };
+                };
+
+                mem-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x90000000 0x90000000 0x10000>;
+
+                        memory-controller@90000000 {
+                                compatible = "sirf,prima2-memc";
+                                reg = <0x90000000 0x10000>;
+                                interrupts = <27>;
+                        };
+                };
+
+                disp-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x90010000 0x90010000 0x30000>;
+
+                        display@90010000 {
+                                compatible = "sirf,prima2-lcd";
+                                reg = <0x90010000 0x20000>;
+                                interrupts = <30>;
+                        };
+
+                        vpp@90020000 {
+                                compatible = "sirf,prima2-vpp";
+                                reg = <0x90020000 0x10000>;
+                                interrupts = <31>;
+                        };
+                };
+
+                graphics-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x98000000 0x98000000 0x8000000>;
+
+                        graphics@98000000 {
+                                compatible = "powervr,sgx531";
+                                reg = <0x98000000 0x8000000>;
+                                interrupts = <6>;
+                        };
+                };
+
+                multimedia-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xa0000000 0xa0000000 0x8000000>;
+
+                        multimedia@a0000000 {
+                                compatible = "sirf,prima2-video-codec";
+                                reg = <0xa0000000 0x8000000>;
+                                interrupts = <5>;
+                        };
+                };
+
+                dsp-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xa8000000 0xa8000000 0x2000000>;
+
+                        dspif@a8000000 {
+                                compatible = "sirf,prima2-dspif";
+                                reg = <0xa8000000 0x10000>;
+                                interrupts = <9>;
+                        };
+
+                        gps@a8010000 {
+                                compatible = "sirf,prima2-gps";
+                                reg = <0xa8010000 0x10000>;
+                                interrupts = <7>;
+                        };
+
+                        dsp@a9000000 {
+                                compatible = "sirf,prima2-dsp";
+                                reg = <0xa9000000 0x1000000>;
+                                interrupts = <8>;
+                        };
+                };
+
+                peri-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xb0000000 0xb0000000 0x180000>;
+
+                        timer@b0020000 {
+                                compatible = "sirf,prima2-tick";
+                                reg = <0xb0020000 0x1000>;
+                                interrupts = <0>;
+                        };
+
+                        nand@b0030000 {
+                                compatible = "sirf,prima2-nand";
+                                reg = <0xb0030000 0x10000>;
+                                interrupts = <41>;
+                        };
+
+                        audio@b0040000 {
+                                compatible = "sirf,prima2-audio";
+                                reg = <0xb0040000 0x10000>;
+                                interrupts = <35>;
+                        };
+
+                        uart0: uart@b0050000 {
+                                cell-index = <0>;
+                                compatible = "sirf,prima2-uart";
+                                reg = <0xb0050000 0x10000>;
+                                interrupts = <17>;
+                        };
+
+                        uart1: uart@b0060000 {
+                                cell-index = <1>;
+                                compatible = "sirf,prima2-uart";
+                                reg = <0xb0060000 0x10000>;
+                                interrupts = <18>;
+                        };
+
+                        uart2: uart@b0070000 {
+                                cell-index = <2>;
+                                compatible = "sirf,prima2-uart";
+                                reg = <0xb0070000 0x10000>;
+                                interrupts = <19>;
+                        };
+
+                        usp0: usp@b0080000 {
+                                cell-index = <0>;
+                                compatible = "sirf,prima2-usp";
+                                reg = <0xb0080000 0x10000>;
+                                interrupts = <20>;
+                        };
+
+                        usp1: usp@b0090000 {
+                                cell-index = <1>;
+                                compatible = "sirf,prima2-usp";
+                                reg = <0xb0090000 0x10000>;
+                                interrupts = <21>;
+                        };
+
+                        usp2: usp@b00a0000 {
+                                cell-index = <2>;
+                                compatible = "sirf,prima2-usp";
+                                reg = <0xb00a0000 0x10000>;
+                                interrupts = <22>;
+                        };
+
+                        dmac0: dma-controller@b00b0000 {
+                                cell-index = <0>;
+                                compatible = "sirf,prima2-dmac";
+                                reg = <0xb00b0000 0x10000>;
+                                interrupts = <12>;
+                        };
+
+                        dmac1: dma-controller@b0160000 {
+                                cell-index = <1>;
+                                compatible = "sirf,prima2-dmac";
+                                reg = <0xb0160000 0x10000>;
+                                interrupts = <13>;
+                        };
+
+                        vip@b00C0000 {
+                                compatible = "sirf,prima2-vip";
+                                reg = <0xb00C0000 0x10000>;
+                        };
+
+                        spi0: spi@b00d0000 {
+                                cell-index = <0>;
+                                compatible = "sirf,prima2-spi";
+                                reg = <0xb00d0000 0x10000>;
+                                interrupts = <15>;
+                        };
+
+                        spi1: spi@b0170000 {
+                                cell-index = <1>;
+                                compatible = "sirf,prima2-spi";
+                                reg = <0xb0170000 0x10000>;
+                                interrupts = <16>;
+                        };
+
+                        i2c0: i2c@b00e0000 {
+                                cell-index = <0>;
+                                compatible = "sirf,prima2-i2c";
+                                reg = <0xb00e0000 0x10000>;
+                                interrupts = <24>;
+                        };
+
+                        i2c1: i2c@b00f0000 {
+                                cell-index = <1>;
+                                compatible = "sirf,prima2-i2c";
+                                reg = <0xb00f0000 0x10000>;
+                                interrupts = <25>;
+                        };
+
+                        tsc@b0110000 {
+                                compatible = "sirf,prima2-tsc";
+                                reg = <0xb0110000 0x10000>;
+                                interrupts = <33>;
+                        };
+
+                        gpio: gpio-controller@b0120000 {
+                                #gpio-cells = <2>;
+                                #interrupt-cells = <2>;
+                                compatible = "sirf,prima2-gpio";
+                                reg = <0xb0120000 0x10000>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+
+                        pwm@b0130000 {
+                                compatible = "sirf,prima2-pwm";
+                                reg = <0xb0130000 0x10000>;
+                        };
+
+                        efusesys@b0140000 {
+                                compatible = "sirf,prima2-efuse";
+                                reg = <0xb0140000 0x10000>;
+                        };
+
+                        pulsec@b0150000 {
+                                compatible = "sirf,prima2-pulsec";
+                                reg = <0xb0150000 0x10000>;
+                                interrupts = <48>;
+                        };
+
+                        pci-iobg {
+                                compatible = "sirf,prima2-pciiobg", "simple-bus";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0x56000000 0x56000000 0x1b00000>;
+
+                                sd0: sdhci@56000000 {
+                                        cell-index = <0>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56000000 0x100000>;
+                                        interrupts = <38>;
+                                };
+
+                                sd1: sdhci@56100000 {
+                                        cell-index = <1>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56100000 0x100000>;
+                                        interrupts = <38>;
+                                };
+
+                                sd2: sdhci@56200000 {
+                                        cell-index = <2>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56200000 0x100000>;
+                                        interrupts = <23>;
+                                };
+
+                                sd3: sdhci@56300000 {
+                                        cell-index = <3>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56300000 0x100000>;
+                                        interrupts = <23>;
+                                };
+
+                                sd4: sdhci@56400000 {
+                                        cell-index = <4>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56400000 0x100000>;
+                                        interrupts = <39>;
+                                };
+
+                                sd5: sdhci@56500000 {
+                                        cell-index = <5>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56500000 0x100000>;
+                                        interrupts = <39>;
+                                };
+
+                                pci-copy@57900000 {
+                                        compatible = "sirf,prima2-pcicp";
+                                        reg = <0x57900000 0x100000>;
+                                        interrupts = <40>;
+                                };
+
+                                rom-interface@57a00000 {
+                                        compatible = "sirf,prima2-romif";
+                                        reg = <0x57a00000 0x100000>;
+                                };
+                        };
+                };
+
+                rtc-iobg {
+                        compatible = "sirf,prima2-rtciobg", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x80030000 0x10000>;
+
+                        gpsrtc@1000 {
+                                compatible = "sirf,prima2-gpsrtc";
+                                reg = <0x1000 0x1000>;
+                                interrupts = <55 56 57>;
+                        };
+
+                        sysrtc@2000 {
+                                compatible = "sirf,prima2-sysrtc";
+                                reg = <0x2000 0x1000>;
+                                interrupts = <52 53 54>;
+                        };
+
+                        pwrc@3000 {
+                                compatible = "sirf,prima2-pwrc";
+                                reg = <0x3000 0x1000>;
+                                interrupts = <32>;
+                        };
+                };
+
+                uus-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xb8000000 0xb8000000 0x40000>;
+
+                        usb0: usb@b00e0000 {
+                                compatible = "chipidea,ci13611a-prima2";
+                                reg = <0xb8000000 0x10000>;
+                                interrupts = <10>;
+                        };
+
+                        usb1: usb@b00f0000 {
+                                compatible = "chipidea,ci13611a-prima2";
+                                reg = <0xb8010000 0x10000>;
+                                interrupts = <11>;
+                        };
+
+                        sata@b00f0000 {
+                                compatible = "synopsys,dwc-ahsata";
+                                reg = <0xb8020000 0x10000>;
+                                interrupts = <37>;
+                        };
+
+                        security@b00f0000 {
+                                compatible = "sirf,prima2-security";
+                                reg = <0xb8030000 0x10000>;
+                                interrupts = <42>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/skeleton.dtsi b/arch/arm/boot/dts/skeleton.dtsi
new file mode 100644
index 000000000000..b41d241de2cd
--- /dev/null
+++ b/arch/arm/boot/dts/skeleton.dtsi
@@ -0,0 +1,13 @@
+/*
+ * Skeleton device tree; the bare minimum needed to boot; just include and
+ * add a compatible value.  The bootloader will typically populate the memory
+ * node.
+ */
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        chosen { };
+        aliases { };
+        memory { device_type = "memory"; reg = <0 0>; };
+};
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts
new file mode 100644
index 000000000000..4c053340ce33
--- /dev/null
+++ b/arch/arm/boot/dts/tegra-harmony.dts
@@ -0,0 +1,70 @@
+/dts-v1/;
+
+/memreserve/ 0x1c000000 0x04000000;
+/include/ "tegra20.dtsi"
+
+/ {
+        model = "NVIDIA Tegra2 Harmony evaluation board";
+        compatible = "nvidia,harmony", "nvidia,tegra20";
+
+        chosen {
+                bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk0p2 rw rootwait";
+        };
+
+        memory@0 {
+                reg = < 0x00000000 0x40000000 >;
+        };
+
+        i2c@7000c000 {
+                clock-frequency = <400000>;
+
+                codec: wm8903@1a {
+                        compatible = "wlf,wm8903";
+                        reg = <0x1a>;
+                        interrupts = < 347 >;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        /* 0x8000 = Not configured */
+                        gpio-cfg = < 0x8000 0x8000 0 0x8000 0x8000 >;
+                };
+        };
+
+        i2c@7000c400 {
+                clock-frequency = <400000>;
+        };
+
+        i2c@7000c500 {
+                clock-frequency = <400000>;
+        };
+
+        i2c@7000d000 {
+                clock-frequency = <400000>;
+        };
+
+        sound {
+                compatible = "nvidia,harmony-sound", "nvidia,tegra-wm8903";
+
+                spkr-en-gpios = <&codec 2 0>;
+                hp-det-gpios = <&gpio 178 0>;
+                int-mic-en-gpios = <&gpio 184 0>;
+                ext-mic-en-gpios = <&gpio 185 0>;
+        };
+
+        serial@70006300 {
+                clock-frequency = < 216000000 >;
+        };
+
+        sdhci@c8000200 {
+                gpios = <&gpio 69 0>, /* cd, gpio PI5 */
+                        <&gpio 57 0>, /* wp, gpio PH1 */
+                        <&gpio 155 0>; /* power, gpio PT3 */
+        };
+
+        sdhci@c8000600 {
+                gpios = <&gpio 58 0>, /* cd, gpio PH2 */
+                        <&gpio 59 0>, /* wp, gpio PH3 */
+                        <&gpio 70 0>; /* power, gpio PI6 */
+        };
+};
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
new file mode 100644
index 000000000000..1940cae00748
--- /dev/null
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -0,0 +1,28 @@
+/dts-v1/;
+
+/memreserve/ 0x1c000000 0x04000000;
+/include/ "tegra20.dtsi"
+
+/ {
+        model = "NVIDIA Seaboard";
+        compatible = "nvidia,seaboard", "nvidia,tegra20";
+
+        chosen {
+                bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = < 0x00000000 0x40000000 >;
+        };
+
+        serial@70006300 {
+                clock-frequency = < 216000000 >;
+        };
+
+        sdhci@c8000400 {
+                gpios = <&gpio 69 0>, /* cd, gpio PI5 */
+                        <&gpio 57 0>, /* wp, gpio PH1 */
+                        <&gpio 70 0>; /* power, gpio PI6 */
+        };
+};
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
new file mode 100644
index 000000000000..5727595cde61
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -0,0 +1,139 @@
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "nvidia,tegra20";
+        interrupt-parent = <&intc>;
+
+        intc: interrupt-controller@50041000 {
+                compatible = "nvidia,tegra20-gic";
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                reg = < 0x50041000 0x1000 >,
+                      < 0x50040100 0x0100 >;
+        };
+
+        i2c@7000c000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "nvidia,tegra20-i2c";
+                reg = <0x7000C000 0x100>;
+                interrupts = < 70 >;
+        };
+
+        i2c@7000c400 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "nvidia,tegra20-i2c";
+                reg = <0x7000C400 0x100>;
+                interrupts = < 116 >;
+        };
+
+        i2c@7000c500 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "nvidia,tegra20-i2c";
+                reg = <0x7000C500 0x100>;
+                interrupts = < 124 >;
+        };
+
+        i2c@7000d000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "nvidia,tegra20-i2c";
+                reg = <0x7000D000 0x200>;
+                interrupts = < 85 >;
+        };
+
+        i2s@70002800 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "nvidia,tegra20-i2s";
+                reg = <0x70002800 0x200>;
+                interrupts = < 45 >;
+                dma-channel = < 2 >;
+        };
+
+        i2s@70002a00 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "nvidia,tegra20-i2s";
+                reg = <0x70002a00 0x200>;
+                interrupts = < 35 >;
+                dma-channel = < 1 >;
+        };
+
+        das@70000c00 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "nvidia,tegra20-das";
+                reg = <0x70000c00 0x80>;
+        };
+
+        gpio: gpio@6000d000 {
+                compatible = "nvidia,tegra20-gpio";
+                reg = < 0x6000d000 0x1000 >;
+                interrupts = < 64 65 66 67 87 119 121 >;
+                #gpio-cells = <2>;
+                gpio-controller;
+        };
+
+        serial@70006000 {
+                compatible = "nvidia,tegra20-uart";
+                reg = <0x70006000 0x40>;
+                reg-shift = <2>;
+                interrupts = < 68 >;
+        };
+
+        serial@70006040 {
+                compatible = "nvidia,tegra20-uart";
+                reg = <0x70006040 0x40>;
+                reg-shift = <2>;
+                interrupts = < 69 >;
+        };
+
+        serial@70006200 {
+                compatible = "nvidia,tegra20-uart";
+                reg = <0x70006200 0x100>;
+                reg-shift = <2>;
+                interrupts = < 78 >;
+        };
+
+        serial@70006300 {
+                compatible = "nvidia,tegra20-uart";
+                reg = <0x70006300 0x100>;
+                reg-shift = <2>;
+                interrupts = < 122 >;
+        };
+
+        serial@70006400 {
+                compatible = "nvidia,tegra20-uart";
+                reg = <0x70006400 0x100>;
+                reg-shift = <2>;
+                interrupts = < 123 >;
+        };
+
+        sdhci@c8000000 {
+                compatible = "nvidia,tegra20-sdhci";
+                reg = <0xc8000000 0x200>;
+                interrupts = < 46 >;
+        };
+
+        sdhci@c8000200 {
+                compatible = "nvidia,tegra20-sdhci";
+                reg = <0xc8000200 0x200>;
+                interrupts = < 47 >;
+        };
+
+        sdhci@c8000400 {
+                compatible = "nvidia,tegra20-sdhci";
+                reg = <0xc8000400 0x200>;
+                interrupts = < 51 >;
+        };
+
+        sdhci@c8000600 {
+                compatible = "nvidia,tegra20-sdhci";
+                reg = <0xc8000600 0x200>;
+                interrupts = < 63 >;
+        };
+};
+
diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts
new file mode 100644
index 000000000000..0b32925f2147
--- /dev/null
+++ b/arch/arm/boot/dts/versatile-ab.dts
@@ -0,0 +1,192 @@
+/dts-v1/;
+/include/ "skeleton.dtsi"
+
+/ {
+        model = "ARM Versatile AB";
+        compatible = "arm,versatile-ab";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        interrupt-parent = <&vic>;
+
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                i2c0 = &i2c0;
+        };
+
+        memory {
+                reg = <0x0 0x08000000>;
+        };
+
+        flash@34000000 {
+                compatible = "arm,versatile-flash";
+                reg = <0x34000000 0x4000000>;
+                bank-width = <4>;
+        };
+
+        i2c0: i2c@10002000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "arm,versatile-i2c";
+                reg = <0x10002000 0x1000>;
+
+                rtc@68 {
+                        compatible = "dallas,ds1338";
+                        reg = <0x68>;
+                };
+        };
+
+        net@10010000 {
+                compatible = "smsc,lan91c111";
+                reg = <0x10010000 0x10000>;
+                interrupts = <25>;
+        };
+
+        lcd@10008000 {
+                compatible = "arm,versatile-lcd";
+                reg = <0x10008000 0x1000>;
+        };
+
+        amba {
+                compatible = "arm,amba-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                vic: intc@10140000 {
+                        compatible = "arm,versatile-vic";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        reg = <0x10140000 0x1000>;
+                };
+
+                sic: intc@10003000 {
+                        compatible = "arm,versatile-sic";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        reg = <0x10003000 0x1000>;
+                        interrupt-parent = <&vic>;
+                        interrupts = <31>; /* Cascaded to vic */
+                };
+
+                dma@10130000 {
+                        compatible = "arm,pl081", "arm,primecell";
+                        reg = <0x10130000 0x1000>;
+                        interrupts = <17>;
+                };
+
+                uart0: uart@101f1000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0x101f1000 0x1000>;
+                        interrupts = <12>;
+                };
+
+                uart1: uart@101f2000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0x101f2000 0x1000>;
+                        interrupts = <13>;
+                };
+
+                uart2: uart@101f3000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0x101f3000 0x1000>;
+                        interrupts = <14>;
+                };
+
+                smc@10100000 {
+                        compatible = "arm,primecell";
+                        reg = <0x10100000 0x1000>;
+                };
+
+                mpmc@10110000 {
+                        compatible = "arm,primecell";
+                        reg = <0x10110000 0x1000>;
+                };
+
+                display@10120000 {
+                        compatible = "arm,pl110", "arm,primecell";
+                        reg = <0x10120000 0x1000>;
+                        interrupts = <16>;
+                };
+
+                sctl@101e0000 {
+                        compatible = "arm,primecell";
+                        reg = <0x101e0000 0x1000>;
+                };
+
+                watchdog@101e1000 {
+                        compatible = "arm,primecell";
+                        reg = <0x101e1000 0x1000>;
+                        interrupts = <0>;
+                };
+
+                gpio0: gpio@101e4000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x101e4000 0x1000>;
+                        gpio-controller;
+                        interrupts = <6>;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpio1: gpio@101e5000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x101e5000 0x1000>;
+                        interrupts = <7>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                rtc@101e8000 {
+                        compatible = "arm,pl030", "arm,primecell";
+                        reg = <0x101e8000 0x1000>;
+                        interrupts = <10>;
+                };
+
+                sci@101f0000 {
+                        compatible = "arm,primecell";
+                        reg = <0x101f0000 0x1000>;
+                        interrupts = <15>;
+                };
+
+                ssp@101f4000 {
+                        compatible = "arm,pl022", "arm,primecell";
+                        reg = <0x101f4000 0x1000>;
+                        interrupts = <11>;
+                };
+
+                fpga {
+                        compatible = "arm,versatile-fpga", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x10000000 0x10000>;
+
+                        aaci@4000 {
+                                compatible = "arm,primecell";
+                                reg = <0x4000 0x1000>;
+                                interrupts = <24>;
+                        };
+                        mmc@5000 {
+                                compatible = "arm,primecell";
+                                reg = < 0x5000 0x1000>;
+                                interrupts = <22>;
+                        };
+                        kmi@6000 {
+                                compatible = "arm,pl050", "arm,primecell";
+                                reg = <0x6000 0x1000>;
+                                interrupt-parent = <&sic>;
+                                interrupts = <3>;
+                        };
+                        kmi@7000 {
+                                compatible = "arm,pl050", "arm,primecell";
+                                reg = <0x7000 0x1000>;
+                                interrupt-parent = <&sic>;
+                                interrupts = <4>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/versatile-pb.dts
new file mode 100644
index 000000000000..8a614e398004
--- /dev/null
+++ b/arch/arm/boot/dts/versatile-pb.dts
@@ -0,0 +1,48 @@
+/include/ "versatile-ab.dts"
+
+/ {
+        model = "ARM Versatile PB";
+        compatible = "arm,versatile-pb";
+
+        amba {
+                gpio2: gpio@101e6000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x101e6000 0x1000>;
+                        interrupts = <8>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpio3: gpio@101e7000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x101e7000 0x1000>;
+                        interrupts = <9>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                fpga {
+                        uart@9000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x9000 0x1000>;
+                                interrupt-parent = <&sic>;
+                                interrupts = <6>;
+                        };
+                        sci@a000 {
+                                compatible = "arm,primecell";
+                                reg = <0xa000 0x1000>;
+                                interrupt-parent = <&sic>;
+                                interrupts = <5>;
+                        };
+                        mmc@b000 {
+                                compatible = "arm,primecell";
+                                reg = <0xb000 0x1000>;
+                                interrupts = <23>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/zynq-ep107.dts b/arch/arm/boot/dts/zynq-ep107.dts
new file mode 100644
index 000000000000..37ca192fb193
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-ep107.dts
@@ -0,0 +1,52 @@
+/*
+ *  Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/ {
+        model = "Xilinx Zynq EP107";
+        compatible = "xlnx,zynq-ep107";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        interrupt-parent = <&intc>;
+
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x10000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyPS0,9600 root=/dev/ram rw initrd=0x800000,8M earlyprintk";
+                linux,stdout-path = &uart0;
+        };
+
+        amba {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                intc: interrupt-controller@f8f01000 {
+                        interrupt-controller;
+                        compatible = "arm,gic";
+                        reg = <0xF8F01000 0x1000>;
+                        #interrupt-cells = <2>;
+                };
+
+                uart0: uart@e0000000 {
+                        compatible = "xlnx,xuartps";
+                        reg = <0xE0000000 0x1000>;
+                        interrupts = <59 0>;
+                        clock = <50000000>;
+                };
+        };
+};