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author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-07-02 18:04:12 -0400 |
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committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-07-02 18:04:12 -0400 |
commit | a8c4c20dfa8b28a3c99e33c639d9c2ea5657741e (patch) | |
tree | 887b64d29b5a46d9ab2ca1267d8a2f05b5845561 /arch/arm/boot | |
parent | 168d04b3b4de7723eb73b3cffc9cb75224e0f393 (diff) | |
parent | 2dc7667b9d0674db6572723356fe3857031101a4 (diff) |
Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (44 commits)
[ARM] 3541/2: workaround for PXA27x erratum E7
[ARM] nommu: provide a way for correct control register value selection
[ARM] 3705/1: add supersection support to ioremap()
[ARM] 3707/1: iwmmxt: use the generic thread notifier infrastructure
[ARM] 3706/2: ep93xx: add cirrus logic edb9315a support
[ARM] 3704/1: format IOP Kconfig with tabs, create more consistency
[ARM] 3703/1: Add help description for ARCH_EP80219
[ARM] 3678/1: MMC: Make OMAP MMC work
[ARM] 3677/1: OMAP: Update H2 defconfig
[ARM] 3676/1: ARM: OMAP: Fix dmtimers and timer32k to compile on OMAP1
[ARM] Add section support to ioremap
[ARM] Fix sa11x0 SDRAM selection
[ARM] Set bit 4 on section mappings correctly depending on CPU
[ARM] 3666/1: TRIZEPS4 [1/5] core
ARM: OMAP: Multiplexing for 24xx GPMC wait pin monitoring
ARM: OMAP: Fix SRAM to use MT_MEMORY instead of MT_DEVICE
ARM: OMAP: Update dmtimers
ARM: OMAP: Make clock variables static
ARM: OMAP: Fix GPMC compilation when DEBUG is defined
ARM: OMAP: Mux updates for external DMA and GPIO
...
Diffstat (limited to 'arch/arm/boot')
-rw-r--r-- | arch/arm/boot/compressed/head.S | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index f7b5c6db30f5..14a9ff9c68df 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S | |||
@@ -447,8 +447,11 @@ __common_mmu_cache_on: | |||
447 | mov r1, #-1 | 447 | mov r1, #-1 |
448 | mcr p15, 0, r3, c2, c0, 0 @ load page table pointer | 448 | mcr p15, 0, r3, c2, c0, 0 @ load page table pointer |
449 | mcr p15, 0, r1, c3, c0, 0 @ load domain access control | 449 | mcr p15, 0, r1, c3, c0, 0 @ load domain access control |
450 | mcr p15, 0, r0, c1, c0, 0 @ load control register | 450 | b 1f |
451 | mov pc, lr | 451 | .align 5 @ cache line aligned |
452 | 1: mcr p15, 0, r0, c1, c0, 0 @ load control register | ||
453 | mrc p15, 0, r0, c1, c0, 0 @ and read it back to | ||
454 | sub pc, lr, r0, lsr #32 @ properly flush pipeline | ||
452 | 455 | ||
453 | /* | 456 | /* |
454 | * All code following this line is relocatable. It is relocated by | 457 | * All code following this line is relocatable. It is relocated by |