Merge branch 'devel'

* devel: (33 commits)
  edac i5000, i5400: fix pointer math in i5000_get_mc_regs()
  edac: allow specifying the error count with fake_inject
  edac: add support for Calxeda highbank L2 cache ecc
  edac: add support for Calxeda highbank memory controller
  edac: create top-level debugfs directory
  sb_edac: properly handle error count
  i7core_edac: properly handle error count
  edac: edac_mc_handle_error(): add an error_count parameter
  edac: remove arch-specific parameter for the error handler
  amd64_edac: Don't pass driver name as an error parameter
  edac_mc: check for allocation failure in edac_mc_alloc()
  edac: Increase version to 3.0.0
  edac_mc: Cleanup per-dimm_info debug messages
  edac: Convert debugfX to edac_dbg(X,
  edac: Use more normal debugging macro style
  edac: Don't add __func__ or __FILE__ for debugf[0-9] msgs
  Edac: Add ABI Documentation for the new device nodes
  edac: move documentation ABI to ABI/testing/sysfs-devices-edac
  i7core_edac: change the mem allocation scheme to make Documentation/kobject.txt happy
  edac: change the mem allocation scheme to make Documentation/kobject.txt happy
  ...

1 files changed, 12 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
index 83e72294aefb..4d641ea4e271 100644
--- a/arch/arm/boot/dts/highbank.dts
+++ b/arch/arm/boot/dts/highbank.dts
@@ -118,6 +118,12 @@
                         interrupts = <0 90 4>;
                 };
 
+                memory-controller@fff00000 {
+                        compatible = "calxeda,hb-ddr-ctrl";
+                        reg = <0xfff00000 0x1000>;
+                        interrupts = <0 91 4>;
+                };
+
                 ipc@fff20000 {
                         compatible = "arm,pl320", "arm,primecell";
                         reg = <0xfff20000 0x1000>;
@@ -188,6 +194,12 @@
                         reg = <0xfff3c000 0x1000>;
                 };
 
+                sregs@fff3c200 {
+                        compatible = "calxeda,hb-sregs-l2-ecc";
+                        reg = <0xfff3c200 0x100>;
+                        interrupts = <0 71 4  0 72 4>;
+                };
+
                 dma@fff3d000 {
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0xfff3d000 0x1000>;