diff options
author | Nicolas Pitre <nico@cam.org> | 2006-07-01 16:29:32 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-07-01 16:29:32 -0400 |
commit | 2dc7667b9d0674db6572723356fe3857031101a4 (patch) | |
tree | 39a69f5928bd052de309ffc4df288642f70b0f89 /arch/arm/boot | |
parent | 3f8efdbe73a5bc96e006b2379a8c8d1d8ef52a9d (diff) |
[ARM] 3541/2: workaround for PXA27x erratum E7
Patch from Nicolas Pitre
According to the Intel PXA27x Processor Family Specification
Update document (doc.nr. 280071-009) erratum E7, some care must be taken
to locate the disabling and re-enabling of the MMU to the beginning of a
cache line to avoid problems in some circumstances.
Credits to Simon Vogl <simon.vogl@researchstudios.at> for bringing this
up.
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r-- | arch/arm/boot/compressed/head.S | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 23016f6aa645..9b42b88bfba0 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S | |||
@@ -448,8 +448,11 @@ __common_mmu_cache_on: | |||
448 | mov r1, #-1 | 448 | mov r1, #-1 |
449 | mcr p15, 0, r3, c2, c0, 0 @ load page table pointer | 449 | mcr p15, 0, r3, c2, c0, 0 @ load page table pointer |
450 | mcr p15, 0, r1, c3, c0, 0 @ load domain access control | 450 | mcr p15, 0, r1, c3, c0, 0 @ load domain access control |
451 | mcr p15, 0, r0, c1, c0, 0 @ load control register | 451 | b 1f |
452 | mov pc, lr | 452 | .align 5 @ cache line aligned |
453 | 1: mcr p15, 0, r0, c1, c0, 0 @ load control register | ||
454 | mrc p15, 0, r0, c1, c0, 0 @ and read it back to | ||
455 | sub pc, lr, r0, lsr #32 @ properly flush pipeline | ||
453 | 456 | ||
454 | /* | 457 | /* |
455 | * All code following this line is relocatable. It is relocated by | 458 | * All code following this line is relocatable. It is relocated by |