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authorOlof Johansson <olof@lixom.net>2014-05-30 23:32:48 -0400
committerOlof Johansson <olof@lixom.net>2014-05-30 23:32:48 -0400
commitbb195016513513c78954678c22d30a4b2d4a6b1f (patch)
tree1d315ac59099d7b0700b3050f2dab2bdd0b1f050 /arch/arm/boot
parente1134cb6b3b8baa6d5d8dc858b9e71f7a060db4f (diff)
parentf46d23f6f3676720de2a3f195413a5e69f202238 (diff)
Merge tag 'qcom-dt-for-3.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into next/dt
Merge "Qualcomm ARM Based Device Tree Updates for v3.16-2" from Kumar Gala: * Updated MSM8660/MSM8960/MSM8974 dts for various updates or conformitity to binding specs * Added APQ8064 SoC and IFC6410 board device tree support * Added APQ8084 SoC and APQ8084-MTP board device tree support * tag 'qcom-dt-for-3.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom: ARM: dts: qcom: Add APQ8084-MTP board support ARM: dts: qcom: Add APQ8084 SoC support ARM: dts: qcom: Add initial APQ8064 SoC and IFC6410 board device trees ARM: dts: qcom: Update msm8660 device trees ARM: dts: qcom: Update msm8960 device trees ARM: dts: qcom: Update msm8974/apq8074 device trees Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/Makefile9
-rw-r--r--arch/arm/boot/dts/qcom-apq8064-ifc6410.dts16
-rw-r--r--arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi1
-rw-r--r--arch/arm/boot/dts/qcom-apq8064.dtsi170
-rw-r--r--arch/arm/boot/dts/qcom-apq8074-dragonboard.dts28
-rw-r--r--arch/arm/boot/dts/qcom-apq8084-mtp.dts6
-rw-r--r--arch/arm/boot/dts/qcom-apq8084.dtsi179
-rw-r--r--arch/arm/boot/dts/qcom-msm8660-surf.dts10
-rw-r--r--arch/arm/boot/dts/qcom-msm8660.dtsi115
-rw-r--r--arch/arm/boot/dts/qcom-msm8960-cdp.dts10
-rw-r--r--arch/arm/boot/dts/qcom-msm8960.dtsi176
-rw-r--r--arch/arm/boot/dts/qcom-msm8974.dtsi49
12 files changed, 609 insertions, 160 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b350409d5829..33409a3895b5 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -308,9 +308,12 @@ dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-d2-network.dtb \
308 orion5x-maxtor-shared-storage-2.dtb \ 308 orion5x-maxtor-shared-storage-2.dtb \
309 orion5x-rd88f5182-nas.dtb 309 orion5x-rd88f5182-nas.dtb
310dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb 310dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
311dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \ 311dtb-$(CONFIG_ARCH_QCOM) += \
312 qcom-msm8960-cdp.dtb \ 312 qcom-apq8064-ifc6410.dtb \
313 qcom-apq8074-dragonboard.dtb 313 qcom-apq8074-dragonboard.dtb \
314 qcom-apq8084-mtp.dtb \
315 qcom-msm8660-surf.dtb \
316 qcom-msm8960-cdp.dtb
314dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb 317dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
315dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \ 318dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \
316 s3c6410-smdk6410.dtb 319 s3c6410-smdk6410.dtb
diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
new file mode 100644
index 000000000000..7c2441d526bc
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -0,0 +1,16 @@
1#include "qcom-apq8064-v2.0.dtsi"
2
3/ {
4 model = "Qualcomm APQ8064/IFC6410";
5 compatible = "qcom,apq8064-ifc6410", "qcom,apq8064";
6
7 soc {
8 gsbi@16600000 {
9 status = "ok";
10 qcom,mode = <GSBI_PROT_I2C_UART>;
11 serial@16640000 {
12 status = "ok";
13 };
14 };
15 };
16};
diff --git a/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi b/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi
new file mode 100644
index 000000000000..935c3945fc5e
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi
@@ -0,0 +1 @@
#include "qcom-apq8064.dtsi"
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
new file mode 100644
index 000000000000..92bf793622c3
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -0,0 +1,170 @@
1/dts-v1/;
2
3#include "skeleton.dtsi"
4#include <dt-bindings/clock/qcom,gcc-msm8960.h>
5#include <dt-bindings/soc/qcom,gsbi.h>
6
7/ {
8 model = "Qualcomm APQ8064";
9 compatible = "qcom,apq8064";
10 interrupt-parent = <&intc>;
11
12 cpus {
13 #address-cells = <1>;
14 #size-cells = <0>;
15
16 cpu@0 {
17 compatible = "qcom,krait";
18 enable-method = "qcom,kpss-acc-v1";
19 device_type = "cpu";
20 reg = <0>;
21 next-level-cache = <&L2>;
22 qcom,acc = <&acc0>;
23 qcom,saw = <&saw0>;
24 };
25
26 cpu@1 {
27 compatible = "qcom,krait";
28 enable-method = "qcom,kpss-acc-v1";
29 device_type = "cpu";
30 reg = <1>;
31 next-level-cache = <&L2>;
32 qcom,acc = <&acc1>;
33 qcom,saw = <&saw1>;
34 };
35
36 cpu@2 {
37 compatible = "qcom,krait";
38 enable-method = "qcom,kpss-acc-v1";
39 device_type = "cpu";
40 reg = <2>;
41 next-level-cache = <&L2>;
42 qcom,acc = <&acc2>;
43 qcom,saw = <&saw2>;
44 };
45
46 cpu@3 {
47 compatible = "qcom,krait";
48 enable-method = "qcom,kpss-acc-v1";
49 device_type = "cpu";
50 reg = <3>;
51 next-level-cache = <&L2>;
52 qcom,acc = <&acc3>;
53 qcom,saw = <&saw3>;
54 };
55
56 L2: l2-cache {
57 compatible = "cache";
58 cache-level = <2>;
59 };
60 };
61
62 cpu-pmu {
63 compatible = "qcom,krait-pmu";
64 interrupts = <1 10 0x304>;
65 };
66
67 soc: soc {
68 #address-cells = <1>;
69 #size-cells = <1>;
70 ranges;
71 compatible = "simple-bus";
72
73 intc: interrupt-controller@2000000 {
74 compatible = "qcom,msm-qgic2";
75 interrupt-controller;
76 #interrupt-cells = <3>;
77 reg = <0x02000000 0x1000>,
78 <0x02002000 0x1000>;
79 };
80
81 timer@200a000 {
82 compatible = "qcom,kpss-timer", "qcom,msm-timer";
83 interrupts = <1 1 0x301>,
84 <1 2 0x301>,
85 <1 3 0x301>;
86 reg = <0x0200a000 0x100>;
87 clock-frequency = <27000000>,
88 <32768>;
89 cpu-offset = <0x80000>;
90 };
91
92 acc0: clock-controller@2088000 {
93 compatible = "qcom,kpss-acc-v1";
94 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
95 };
96
97 acc1: clock-controller@2098000 {
98 compatible = "qcom,kpss-acc-v1";
99 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
100 };
101
102 acc2: clock-controller@20a8000 {
103 compatible = "qcom,kpss-acc-v1";
104 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
105 };
106
107 acc3: clock-controller@20b8000 {
108 compatible = "qcom,kpss-acc-v1";
109 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
110 };
111
112 saw0: regulator@2089000 {
113 compatible = "qcom,saw2";
114 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
115 regulator;
116 };
117
118 saw1: regulator@2099000 {
119 compatible = "qcom,saw2";
120 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
121 regulator;
122 };
123
124 saw2: regulator@20a9000 {
125 compatible = "qcom,saw2";
126 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
127 regulator;
128 };
129
130 saw3: regulator@20b9000 {
131 compatible = "qcom,saw2";
132 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
133 regulator;
134 };
135
136 gsbi7: gsbi@16600000 {
137 status = "disabled";
138 compatible = "qcom,gsbi-v1.0.0";
139 reg = <0x16600000 0x100>;
140 clocks = <&gcc GSBI7_H_CLK>;
141 clock-names = "iface";
142 #address-cells = <1>;
143 #size-cells = <1>;
144 ranges;
145
146 serial@16640000 {
147 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
148 reg = <0x16640000 0x1000>,
149 <0x16600000 0x1000>;
150 interrupts = <0 158 0x0>;
151 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
152 clock-names = "core", "iface";
153 status = "disabled";
154 };
155 };
156
157 qcom,ssbi@500000 {
158 compatible = "qcom,ssbi";
159 reg = <0x00500000 0x1000>;
160 qcom,controller-type = "pmic-arbiter";
161 };
162
163 gcc: clock-controller@900000 {
164 compatible = "qcom,gcc-apq8064";
165 reg = <0x00900000 0x4000>;
166 #clock-cells = <1>;
167 #reset-cells = <1>;
168 };
169 };
170};
diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
index 92320c4a7668..b4dfb01fe6fb 100644
--- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
+++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
@@ -4,7 +4,11 @@
4 model = "Qualcomm APQ8074 Dragonboard"; 4 model = "Qualcomm APQ8074 Dragonboard";
5 compatible = "qcom,apq8074-dragonboard", "qcom,apq8074"; 5 compatible = "qcom,apq8074-dragonboard", "qcom,apq8074";
6 6
7 soc: soc { 7 soc {
8 serial@f991e000 {
9 status = "ok";
10 };
11
8 sdhci@f9824900 { 12 sdhci@f9824900 {
9 bus-width = <8>; 13 bus-width = <8>;
10 non-removable; 14 non-removable;
@@ -15,5 +19,27 @@
15 cd-gpios = <&msmgpio 62 0x1>; 19 cd-gpios = <&msmgpio 62 0x1>;
16 bus-width = <4>; 20 bus-width = <4>;
17 }; 21 };
22
23
24 pinctrl@fd510000 {
25 spi8_default: spi8_default {
26 mosi {
27 pins = "gpio45";
28 function = "blsp_spi8";
29 };
30 miso {
31 pins = "gpio46";
32 function = "blsp_spi8";
33 };
34 cs {
35 pins = "gpio47";
36 function = "blsp_spi8";
37 };
38 clk {
39 pins = "gpio48";
40 function = "blsp_spi8";
41 };
42 };
43 };
18 }; 44 };
19}; 45};
diff --git a/arch/arm/boot/dts/qcom-apq8084-mtp.dts b/arch/arm/boot/dts/qcom-apq8084-mtp.dts
new file mode 100644
index 000000000000..9dae3878b71d
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8084-mtp.dts
@@ -0,0 +1,6 @@
1#include "qcom-apq8084.dtsi"
2
3/ {
4 model = "Qualcomm APQ 8084-MTP";
5 compatible = "qcom,apq8084-mtp", "qcom,apq8084";
6};
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
new file mode 100644
index 000000000000..e3e009a5912b
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -0,0 +1,179 @@
1/dts-v1/;
2
3#include "skeleton.dtsi"
4
5/ {
6 model = "Qualcomm APQ 8084";
7 compatible = "qcom,apq8084";
8 interrupt-parent = <&intc>;
9
10 cpus {
11 #address-cells = <1>;
12 #size-cells = <0>;
13
14 cpu@0 {
15 device_type = "cpu";
16 compatible = "qcom,krait";
17 reg = <0>;
18 enable-method = "qcom,kpss-acc-v2";
19 next-level-cache = <&L2>;
20 qcom,acc = <&acc0>;
21 };
22
23 cpu@1 {
24 device_type = "cpu";
25 compatible = "qcom,krait";
26 reg = <1>;
27 enable-method = "qcom,kpss-acc-v2";
28 next-level-cache = <&L2>;
29 qcom,acc = <&acc1>;
30 };
31
32 cpu@2 {
33 device_type = "cpu";
34 compatible = "qcom,krait";
35 reg = <2>;
36 enable-method = "qcom,kpss-acc-v2";
37 next-level-cache = <&L2>;
38 qcom,acc = <&acc2>;
39 };
40
41 cpu@3 {
42 device_type = "cpu";
43 compatible = "qcom,krait";
44 reg = <3>;
45 enable-method = "qcom,kpss-acc-v2";
46 next-level-cache = <&L2>;
47 qcom,acc = <&acc3>;
48 };
49
50 L2: l2-cache {
51 compatible = "qcom,arch-cache";
52 cache-level = <2>;
53 qcom,saw = <&saw_l2>;
54 };
55 };
56
57 cpu-pmu {
58 compatible = "qcom,krait-pmu";
59 interrupts = <1 7 0xf04>;
60 };
61
62 timer {
63 compatible = "arm,armv7-timer";
64 interrupts = <1 2 0xf08>,
65 <1 3 0xf08>,
66 <1 4 0xf08>,
67 <1 1 0xf08>;
68 clock-frequency = <19200000>;
69 };
70
71 soc: soc {
72 #address-cells = <1>;
73 #size-cells = <1>;
74 ranges;
75 compatible = "simple-bus";
76
77 intc: interrupt-controller@f9000000 {
78 compatible = "qcom,msm-qgic2";
79 interrupt-controller;
80 #interrupt-cells = <3>;
81 reg = <0xf9000000 0x1000>,
82 <0xf9002000 0x1000>;
83 };
84
85 timer@f9020000 {
86 #address-cells = <1>;
87 #size-cells = <1>;
88 ranges;
89 compatible = "arm,armv7-timer-mem";
90 reg = <0xf9020000 0x1000>;
91 clock-frequency = <19200000>;
92
93 frame@f9021000 {
94 frame-number = <0>;
95 interrupts = <0 8 0x4>,
96 <0 7 0x4>;
97 reg = <0xf9021000 0x1000>,
98 <0xf9022000 0x1000>;
99 };
100
101 frame@f9023000 {
102 frame-number = <1>;
103 interrupts = <0 9 0x4>;
104 reg = <0xf9023000 0x1000>;
105 status = "disabled";
106 };
107
108 frame@f9024000 {
109 frame-number = <2>;
110 interrupts = <0 10 0x4>;
111 reg = <0xf9024000 0x1000>;
112 status = "disabled";
113 };
114
115 frame@f9025000 {
116 frame-number = <3>;
117 interrupts = <0 11 0x4>;
118 reg = <0xf9025000 0x1000>;
119 status = "disabled";
120 };
121
122 frame@f9026000 {
123 frame-number = <4>;
124 interrupts = <0 12 0x4>;
125 reg = <0xf9026000 0x1000>;
126 status = "disabled";
127 };
128
129 frame@f9027000 {
130 frame-number = <5>;
131 interrupts = <0 13 0x4>;
132 reg = <0xf9027000 0x1000>;
133 status = "disabled";
134 };
135
136 frame@f9028000 {
137 frame-number = <6>;
138 interrupts = <0 14 0x4>;
139 reg = <0xf9028000 0x1000>;
140 status = "disabled";
141 };
142 };
143
144 saw_l2: regulator@f9012000 {
145 compatible = "qcom,saw2";
146 reg = <0xf9012000 0x1000>;
147 regulator;
148 };
149
150 acc0: clock-controller@f9088000 {
151 compatible = "qcom,kpss-acc-v2";
152 reg = <0xf9088000 0x1000>,
153 <0xf9008000 0x1000>;
154 };
155
156 acc1: clock-controller@f9098000 {
157 compatible = "qcom,kpss-acc-v2";
158 reg = <0xf9098000 0x1000>,
159 <0xf9008000 0x1000>;
160 };
161
162 acc2: clock-controller@f90a8000 {
163 compatible = "qcom,kpss-acc-v2";
164 reg = <0xf90a8000 0x1000>,
165 <0xf9008000 0x1000>;
166 };
167
168 acc3: clock-controller@f90b8000 {
169 compatible = "qcom,kpss-acc-v2";
170 reg = <0xf90b8000 0x1000>,
171 <0xf9008000 0x1000>;
172 };
173
174 restart@fc4ab000 {
175 compatible = "qcom,pshold";
176 reg = <0xfc4ab000 0x4>;
177 };
178 };
179};
diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts
index 169bad90dac9..45180adfadf1 100644
--- a/arch/arm/boot/dts/qcom-msm8660-surf.dts
+++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts
@@ -3,4 +3,14 @@
3/ { 3/ {
4 model = "Qualcomm MSM8660 SURF"; 4 model = "Qualcomm MSM8660 SURF";
5 compatible = "qcom,msm8660-surf", "qcom,msm8660"; 5 compatible = "qcom,msm8660-surf", "qcom,msm8660";
6
7 soc {
8 gsbi@19c00000 {
9 status = "ok";
10 qcom,mode = <GSBI_PROT_I2C_UART>;
11 serial@19c40000 {
12 status = "ok";
13 };
14 };
15 };
6}; 16};
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
index c52a9e964a44..53837aaa2f72 100644
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -3,6 +3,7 @@
3/include/ "skeleton.dtsi" 3/include/ "skeleton.dtsi"
4 4
5#include <dt-bindings/clock/qcom,gcc-msm8660.h> 5#include <dt-bindings/clock/qcom,gcc-msm8660.h>
6#include <dt-bindings/soc/qcom,gsbi.h>
6 7
7/ { 8/ {
8 model = "Qualcomm MSM8660"; 9 model = "Qualcomm MSM8660";
@@ -12,16 +13,18 @@
12 cpus { 13 cpus {
13 #address-cells = <1>; 14 #address-cells = <1>;
14 #size-cells = <0>; 15 #size-cells = <0>;
15 compatible = "qcom,scorpion";
16 enable-method = "qcom,gcc-msm8660";
17 16
18 cpu@0 { 17 cpu@0 {
18 compatible = "qcom,scorpion";
19 enable-method = "qcom,gcc-msm8660";
19 device_type = "cpu"; 20 device_type = "cpu";
20 reg = <0>; 21 reg = <0>;
21 next-level-cache = <&L2>; 22 next-level-cache = <&L2>;
22 }; 23 };
23 24
24 cpu@1 { 25 cpu@1 {
26 compatible = "qcom,scorpion";
27 enable-method = "qcom,gcc-msm8660";
25 device_type = "cpu"; 28 device_type = "cpu";
26 reg = <1>; 29 reg = <1>;
27 next-level-cache = <&L2>; 30 next-level-cache = <&L2>;
@@ -33,55 +36,73 @@
33 }; 36 };
34 }; 37 };
35 38
36 intc: interrupt-controller@2080000 { 39 soc: soc {
37 compatible = "qcom,msm-8660-qgic"; 40 #address-cells = <1>;
38 interrupt-controller; 41 #size-cells = <1>;
39 #interrupt-cells = <3>; 42 ranges;
40 reg = < 0x02080000 0x1000 >, 43 compatible = "simple-bus";
41 < 0x02081000 0x1000 >;
42 };
43 44
44 timer@2000000 { 45 intc: interrupt-controller@2080000 {
45 compatible = "qcom,scss-timer", "qcom,msm-timer"; 46 compatible = "qcom,msm-8660-qgic";
46 interrupts = <1 0 0x301>, 47 interrupt-controller;
47 <1 1 0x301>, 48 #interrupt-cells = <3>;
48 <1 2 0x301>; 49 reg = < 0x02080000 0x1000 >,
49 reg = <0x02000000 0x100>; 50 < 0x02081000 0x1000 >;
50 clock-frequency = <27000000>, 51 };
51 <32768>;
52 cpu-offset = <0x40000>;
53 };
54 52
55 msmgpio: gpio@800000 { 53 timer@2000000 {
56 compatible = "qcom,msm-gpio"; 54 compatible = "qcom,scss-timer", "qcom,msm-timer";
57 reg = <0x00800000 0x4000>; 55 interrupts = <1 0 0x301>,
58 gpio-controller; 56 <1 1 0x301>,
59 #gpio-cells = <2>; 57 <1 2 0x301>;
60 ngpio = <173>; 58 reg = <0x02000000 0x100>;
61 interrupts = <0 16 0x4>; 59 clock-frequency = <27000000>,
62 interrupt-controller; 60 <32768>;
63 #interrupt-cells = <2>; 61 cpu-offset = <0x40000>;
64 }; 62 };
65 63
66 gcc: clock-controller@900000 { 64 msmgpio: gpio@800000 {
67 compatible = "qcom,gcc-msm8660"; 65 compatible = "qcom,msm-gpio";
68 #clock-cells = <1>; 66 reg = <0x00800000 0x4000>;
69 #reset-cells = <1>; 67 gpio-controller;
70 reg = <0x900000 0x4000>; 68 #gpio-cells = <2>;
71 }; 69 ngpio = <173>;
70 interrupts = <0 16 0x4>;
71 interrupt-controller;
72 #interrupt-cells = <2>;
73 };
72 74
73 serial@19c40000 { 75 gcc: clock-controller@900000 {
74 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 76 compatible = "qcom,gcc-msm8660";
75 reg = <0x19c40000 0x1000>, 77 #clock-cells = <1>;
76 <0x19c00000 0x1000>; 78 #reset-cells = <1>;
77 interrupts = <0 195 0x0>; 79 reg = <0x900000 0x4000>;
78 clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; 80 };
79 clock-names = "core", "iface"; 81
80 }; 82 gsbi12: gsbi@19c00000 {
83 compatible = "qcom,gsbi-v1.0.0";
84 reg = <0x19c00000 0x100>;
85 clocks = <&gcc GSBI12_H_CLK>;
86 clock-names = "iface";
87 #address-cells = <1>;
88 #size-cells = <1>;
89 ranges;
81 90
82 qcom,ssbi@500000 { 91 serial@19c40000 {
83 compatible = "qcom,ssbi"; 92 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
84 reg = <0x500000 0x1000>; 93 reg = <0x19c40000 0x1000>,
85 qcom,controller-type = "pmic-arbiter"; 94 <0x19c00000 0x1000>;
95 interrupts = <0 195 0x0>;
96 clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
97 clock-names = "core", "iface";
98 status = "disabled";
99 };
100 };
101
102 qcom,ssbi@500000 {
103 compatible = "qcom,ssbi";
104 reg = <0x500000 0x1000>;
105 qcom,controller-type = "pmic-arbiter";
106 };
86 }; 107 };
87}; 108};
diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
index a58fb88315f6..8f75cc4c8340 100644
--- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
+++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
@@ -3,4 +3,14 @@
3/ { 3/ {
4 model = "Qualcomm MSM8960 CDP"; 4 model = "Qualcomm MSM8960 CDP";
5 compatible = "qcom,msm8960-cdp", "qcom,msm8960"; 5 compatible = "qcom,msm8960-cdp", "qcom,msm8960";
6
7 soc {
8 gsbi@16400000 {
9 status = "ok";
10 qcom,mode = <GSBI_PROT_I2C_UART>;
11 serial@16440000 {
12 status = "ok";
13 };
14 };
15 };
6}; 16};
diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi
index 997b7b94e117..5303e53e34dc 100644
--- a/arch/arm/boot/dts/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
@@ -3,6 +3,7 @@
3/include/ "skeleton.dtsi" 3/include/ "skeleton.dtsi"
4 4
5#include <dt-bindings/clock/qcom,gcc-msm8960.h> 5#include <dt-bindings/clock/qcom,gcc-msm8960.h>
6#include <dt-bindings/soc/qcom,gsbi.h>
6 7
7/ { 8/ {
8 model = "Qualcomm MSM8960"; 9 model = "Qualcomm MSM8960";
@@ -13,10 +14,10 @@
13 #address-cells = <1>; 14 #address-cells = <1>;
14 #size-cells = <0>; 15 #size-cells = <0>;
15 interrupts = <1 14 0x304>; 16 interrupts = <1 14 0x304>;
16 compatible = "qcom,krait";
17 enable-method = "qcom,kpss-acc-v1";
18 17
19 cpu@0 { 18 cpu@0 {
19 compatible = "qcom,krait";
20 enable-method = "qcom,kpss-acc-v1";
20 device_type = "cpu"; 21 device_type = "cpu";
21 reg = <0>; 22 reg = <0>;
22 next-level-cache = <&L2>; 23 next-level-cache = <&L2>;
@@ -25,6 +26,8 @@
25 }; 26 };
26 27
27 cpu@1 { 28 cpu@1 {
29 compatible = "qcom,krait";
30 enable-method = "qcom,kpss-acc-v1";
28 device_type = "cpu"; 31 device_type = "cpu";
29 reg = <1>; 32 reg = <1>;
30 next-level-cache = <&L2>; 33 next-level-cache = <&L2>;
@@ -35,7 +38,6 @@
35 L2: l2-cache { 38 L2: l2-cache {
36 compatible = "cache"; 39 compatible = "cache";
37 cache-level = <2>; 40 cache-level = <2>;
38 interrupts = <0 2 0x4>;
39 }; 41 };
40 }; 42 };
41 43
@@ -45,91 +47,109 @@
45 qcom,no-pc-write; 47 qcom,no-pc-write;
46 }; 48 };
47 49
48 intc: interrupt-controller@2000000 { 50 soc: soc {
49 compatible = "qcom,msm-qgic2"; 51 #address-cells = <1>;
50 interrupt-controller; 52 #size-cells = <1>;
51 #interrupt-cells = <3>; 53 ranges;
52 reg = < 0x02000000 0x1000 >, 54 compatible = "simple-bus";
53 < 0x02002000 0x1000 >; 55
54 }; 56 intc: interrupt-controller@2000000 {
57 compatible = "qcom,msm-qgic2";
58 interrupt-controller;
59 #interrupt-cells = <3>;
60 reg = <0x02000000 0x1000>,
61 <0x02002000 0x1000>;
62 };
55 63
56 timer@200a000 { 64 timer@200a000 {
57 compatible = "qcom,kpss-timer", "qcom,msm-timer"; 65 compatible = "qcom,kpss-timer", "qcom,msm-timer";
58 interrupts = <1 1 0x301>, 66 interrupts = <1 1 0x301>,
59 <1 2 0x301>, 67 <1 2 0x301>,
60 <1 3 0x301>; 68 <1 3 0x301>;
61 reg = <0x0200a000 0x100>; 69 reg = <0x0200a000 0x100>;
62 clock-frequency = <27000000>, 70 clock-frequency = <27000000>,
63 <32768>; 71 <32768>;
64 cpu-offset = <0x80000>; 72 cpu-offset = <0x80000>;
65 }; 73 };
66 74
67 msmgpio: gpio@800000 { 75 msmgpio: gpio@800000 {
68 compatible = "qcom,msm-gpio"; 76 compatible = "qcom,msm-gpio";
69 gpio-controller; 77 gpio-controller;
70 #gpio-cells = <2>; 78 #gpio-cells = <2>;
71 ngpio = <150>; 79 ngpio = <150>;
72 interrupts = <0 16 0x4>; 80 interrupts = <0 16 0x4>;
73 interrupt-controller; 81 interrupt-controller;
74 #interrupt-cells = <2>; 82 #interrupt-cells = <2>;
75 reg = <0x800000 0x4000>; 83 reg = <0x800000 0x4000>;
76 }; 84 };
77 85
78 gcc: clock-controller@900000 { 86 gcc: clock-controller@900000 {
79 compatible = "qcom,gcc-msm8960"; 87 compatible = "qcom,gcc-msm8960";
80 #clock-cells = <1>; 88 #clock-cells = <1>;
81 #reset-cells = <1>; 89 #reset-cells = <1>;
82 reg = <0x900000 0x4000>; 90 reg = <0x900000 0x4000>;
83 }; 91 };
84 92
85 clock-controller@4000000 { 93 clock-controller@4000000 {
86 compatible = "qcom,mmcc-msm8960"; 94 compatible = "qcom,mmcc-msm8960";
87 reg = <0x4000000 0x1000>; 95 reg = <0x4000000 0x1000>;
88 #clock-cells = <1>; 96 #clock-cells = <1>;
89 #reset-cells = <1>; 97 #reset-cells = <1>;
90 }; 98 };
91 99
92 acc0: clock-controller@2088000 { 100 acc0: clock-controller@2088000 {
93 compatible = "qcom,kpss-acc-v1"; 101 compatible = "qcom,kpss-acc-v1";
94 reg = <0x02088000 0x1000>, <0x02008000 0x1000>; 102 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
95 }; 103 };
96 104
97 acc1: clock-controller@2098000 { 105 acc1: clock-controller@2098000 {
98 compatible = "qcom,kpss-acc-v1"; 106 compatible = "qcom,kpss-acc-v1";
99 reg = <0x02098000 0x1000>, <0x02008000 0x1000>; 107 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
100 }; 108 };
101 109
102 saw0: regulator@2089000 { 110 saw0: regulator@2089000 {
103 compatible = "qcom,saw2"; 111 compatible = "qcom,saw2";
104 reg = <0x02089000 0x1000>, <0x02009000 0x1000>; 112 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
105 regulator; 113 regulator;
106 }; 114 };
107 115
108 saw1: regulator@2099000 { 116 saw1: regulator@2099000 {
109 compatible = "qcom,saw2"; 117 compatible = "qcom,saw2";
110 reg = <0x02099000 0x1000>, <0x02009000 0x1000>; 118 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
111 regulator; 119 regulator;
112 }; 120 };
113 121
114 serial@16440000 { 122 gsbi5: gsbi@16400000 {
115 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 123 compatible = "qcom,gsbi-v1.0.0";
116 reg = <0x16440000 0x1000>, 124 reg = <0x16400000 0x100>;
117 <0x16400000 0x1000>; 125 clocks = <&gcc GSBI5_H_CLK>;
118 interrupts = <0 154 0x0>; 126 clock-names = "iface";
119 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; 127 #address-cells = <1>;
120 clock-names = "core", "iface"; 128 #size-cells = <1>;
121 }; 129 ranges;
130
131 serial@16440000 {
132 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
133 reg = <0x16440000 0x1000>,
134 <0x16400000 0x1000>;
135 interrupts = <0 154 0x0>;
136 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
137 clock-names = "core", "iface";
138 status = "disabled";
139 };
140 };
122 141
123 qcom,ssbi@500000 { 142 qcom,ssbi@500000 {
124 compatible = "qcom,ssbi"; 143 compatible = "qcom,ssbi";
125 reg = <0x500000 0x1000>; 144 reg = <0x500000 0x1000>;
126 qcom,controller-type = "pmic-arbiter"; 145 qcom,controller-type = "pmic-arbiter";
127 }; 146 };
128 147
129 rng@1a500000 { 148 rng@1a500000 {
130 compatible = "qcom,prng"; 149 compatible = "qcom,prng";
131 reg = <0x1a500000 0x200>; 150 reg = <0x1a500000 0x200>;
132 clocks = <&gcc PRNG_CLK>; 151 clocks = <&gcc PRNG_CLK>;
133 clock-names = "core"; 152 clock-names = "core";
153 };
134 }; 154 };
135}; 155};
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index c530a33a10a0..69dca2aca25a 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -13,10 +13,10 @@
13 #address-cells = <1>; 13 #address-cells = <1>;
14 #size-cells = <0>; 14 #size-cells = <0>;
15 interrupts = <1 9 0xf04>; 15 interrupts = <1 9 0xf04>;
16 compatible = "qcom,krait";
17 enable-method = "qcom,kpss-acc-v2";
18 16
19 cpu@0 { 17 cpu@0 {
18 compatible = "qcom,krait";
19 enable-method = "qcom,kpss-acc-v2";
20 device_type = "cpu"; 20 device_type = "cpu";
21 reg = <0>; 21 reg = <0>;
22 next-level-cache = <&L2>; 22 next-level-cache = <&L2>;
@@ -24,6 +24,8 @@
24 }; 24 };
25 25
26 cpu@1 { 26 cpu@1 {
27 compatible = "qcom,krait";
28 enable-method = "qcom,kpss-acc-v2";
27 device_type = "cpu"; 29 device_type = "cpu";
28 reg = <1>; 30 reg = <1>;
29 next-level-cache = <&L2>; 31 next-level-cache = <&L2>;
@@ -31,6 +33,8 @@
31 }; 33 };
32 34
33 cpu@2 { 35 cpu@2 {
36 compatible = "qcom,krait";
37 enable-method = "qcom,kpss-acc-v2";
34 device_type = "cpu"; 38 device_type = "cpu";
35 reg = <2>; 39 reg = <2>;
36 next-level-cache = <&L2>; 40 next-level-cache = <&L2>;
@@ -38,6 +42,8 @@
38 }; 42 };
39 43
40 cpu@3 { 44 cpu@3 {
45 compatible = "qcom,krait";
46 enable-method = "qcom,kpss-acc-v2";
41 device_type = "cpu"; 47 device_type = "cpu";
42 reg = <3>; 48 reg = <3>;
43 next-level-cache = <&L2>; 49 next-level-cache = <&L2>;
@@ -47,7 +53,6 @@
47 L2: l2-cache { 53 L2: l2-cache {
48 compatible = "cache"; 54 compatible = "cache";
49 cache-level = <2>; 55 cache-level = <2>;
50 interrupts = <0 2 0x4>;
51 qcom,saw = <&saw_l2>; 56 qcom,saw = <&saw_l2>;
52 }; 57 };
53 }; 58 };
@@ -57,6 +62,15 @@
57 interrupts = <1 7 0xf04>; 62 interrupts = <1 7 0xf04>;
58 }; 63 };
59 64
65 timer {
66 compatible = "arm,armv7-timer";
67 interrupts = <1 2 0xf08>,
68 <1 3 0xf08>,
69 <1 4 0xf08>,
70 <1 1 0xf08>;
71 clock-frequency = <19200000>;
72 };
73
60 soc: soc { 74 soc: soc {
61 #address-cells = <1>; 75 #address-cells = <1>;
62 #size-cells = <1>; 76 #size-cells = <1>;
@@ -71,15 +85,6 @@
71 <0xf9002000 0x1000>; 85 <0xf9002000 0x1000>;
72 }; 86 };
73 87
74 timer {
75 compatible = "arm,armv7-timer";
76 interrupts = <1 2 0xf08>,
77 <1 3 0xf08>,
78 <1 4 0xf08>,
79 <1 1 0xf08>;
80 clock-frequency = <19200000>;
81 };
82
83 timer@f9020000 { 88 timer@f9020000 {
84 #address-cells = <1>; 89 #address-cells = <1>;
85 #size-cells = <1>; 90 #size-cells = <1>;
@@ -190,6 +195,7 @@
190 interrupts = <0 108 0x0>; 195 interrupts = <0 108 0x0>;
191 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 196 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
192 clock-names = "core", "iface"; 197 clock-names = "core", "iface";
198 status = "disabled";
193 }; 199 };
194 200
195 sdhci@f9824900 { 201 sdhci@f9824900 {
@@ -229,25 +235,6 @@
229 interrupt-controller; 235 interrupt-controller;
230 #interrupt-cells = <2>; 236 #interrupt-cells = <2>;
231 interrupts = <0 208 0>; 237 interrupts = <0 208 0>;
232
233 spi8_default: spi8_default {
234 mosi {
235 pins = "gpio45";
236 function = "blsp_spi8";
237 };
238 miso {
239 pins = "gpio46";
240 function = "blsp_spi8";
241 };
242 cs {
243 pins = "gpio47";
244 function = "blsp_spi8";
245 };
246 clk {
247 pins = "gpio48";
248 function = "blsp_spi8";
249 };
250 };
251 }; 238 };
252 }; 239 };
253}; 240};
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-06 19:45:20 -0400