diff options
author | Alex Elder <elder@linaro.org> | 2014-04-21 17:26:27 -0400 |
---|---|---|
committer | Mike Turquette <mturquette@linaro.org> | 2014-04-30 14:51:45 -0400 |
commit | 8d90c5aff3e8b128fda43aac83b4442048b51bad (patch) | |
tree | 08131f368b7de3fbeea973a13fa679a0b765249a /arch/arm/boot | |
parent | 7d3723ba8c19a9d23a240f8e99010193e5623b06 (diff) |
ARM: dts: use real clocks for bcm21664
Replace the "fake" fixed-rate clocks used previously for the
bcm21664 family with "real" ones.
Signed-off-by: Alex Elder <elder@linaro.org>
Acked-by: Matt Porter <mporter@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r-- | arch/arm/boot/dts/bcm21664.dtsi | 164 |
1 files changed, 105 insertions, 59 deletions
diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi index 08a44d41b672..8b366822bb43 100644 --- a/arch/arm/boot/dts/bcm21664.dtsi +++ b/arch/arm/boot/dts/bcm21664.dtsi | |||
@@ -14,6 +14,8 @@ | |||
14 | #include <dt-bindings/interrupt-controller/arm-gic.h> | 14 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
15 | #include <dt-bindings/interrupt-controller/irq.h> | 15 | #include <dt-bindings/interrupt-controller/irq.h> |
16 | 16 | ||
17 | #include "dt-bindings/clock/bcm21664.h" | ||
18 | |||
17 | #include "skeleton.dtsi" | 19 | #include "skeleton.dtsi" |
18 | 20 | ||
19 | / { | 21 | / { |
@@ -43,7 +45,7 @@ | |||
43 | compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; | 45 | compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; |
44 | status = "disabled"; | 46 | status = "disabled"; |
45 | reg = <0x3e000000 0x118>; | 47 | reg = <0x3e000000 0x118>; |
46 | clocks = <&uartb_clk>; | 48 | clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>; |
47 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; | 49 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
48 | reg-shift = <2>; | 50 | reg-shift = <2>; |
49 | reg-io-width = <4>; | 51 | reg-io-width = <4>; |
@@ -53,7 +55,7 @@ | |||
53 | compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; | 55 | compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; |
54 | status = "disabled"; | 56 | status = "disabled"; |
55 | reg = <0x3e001000 0x118>; | 57 | reg = <0x3e001000 0x118>; |
56 | clocks = <&uartb2_clk>; | 58 | clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>; |
57 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; | 59 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
58 | reg-shift = <2>; | 60 | reg-shift = <2>; |
59 | reg-io-width = <4>; | 61 | reg-io-width = <4>; |
@@ -63,7 +65,7 @@ | |||
63 | compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; | 65 | compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; |
64 | status = "disabled"; | 66 | status = "disabled"; |
65 | reg = <0x3e002000 0x118>; | 67 | reg = <0x3e002000 0x118>; |
66 | clocks = <&uartb3_clk>; | 68 | clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>; |
67 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; | 69 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
68 | reg-shift = <2>; | 70 | reg-shift = <2>; |
69 | reg-io-width = <4>; | 71 | reg-io-width = <4>; |
@@ -85,7 +87,7 @@ | |||
85 | compatible = "brcm,kona-timer"; | 87 | compatible = "brcm,kona-timer"; |
86 | reg = <0x35006000 0x1c>; | 88 | reg = <0x35006000 0x1c>; |
87 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | 89 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
88 | clocks = <&hub_timer_clk>; | 90 | clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>; |
89 | }; | 91 | }; |
90 | 92 | ||
91 | gpio: gpio@35003000 { | 93 | gpio: gpio@35003000 { |
@@ -106,7 +108,7 @@ | |||
106 | compatible = "brcm,kona-sdhci"; | 108 | compatible = "brcm,kona-sdhci"; |
107 | reg = <0x3f180000 0x801c>; | 109 | reg = <0x3f180000 0x801c>; |
108 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | 110 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
109 | clocks = <&sdio1_clk>; | 111 | clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>; |
110 | status = "disabled"; | 112 | status = "disabled"; |
111 | }; | 113 | }; |
112 | 114 | ||
@@ -114,7 +116,7 @@ | |||
114 | compatible = "brcm,kona-sdhci"; | 116 | compatible = "brcm,kona-sdhci"; |
115 | reg = <0x3f190000 0x801c>; | 117 | reg = <0x3f190000 0x801c>; |
116 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; | 118 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
117 | clocks = <&sdio2_clk>; | 119 | clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>; |
118 | status = "disabled"; | 120 | status = "disabled"; |
119 | }; | 121 | }; |
120 | 122 | ||
@@ -122,7 +124,7 @@ | |||
122 | compatible = "brcm,kona-sdhci"; | 124 | compatible = "brcm,kona-sdhci"; |
123 | reg = <0x3f1a0000 0x801c>; | 125 | reg = <0x3f1a0000 0x801c>; |
124 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; | 126 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
125 | clocks = <&sdio3_clk>; | 127 | clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>; |
126 | status = "disabled"; | 128 | status = "disabled"; |
127 | }; | 129 | }; |
128 | 130 | ||
@@ -130,7 +132,7 @@ | |||
130 | compatible = "brcm,kona-sdhci"; | 132 | compatible = "brcm,kona-sdhci"; |
131 | reg = <0x3f1b0000 0x801c>; | 133 | reg = <0x3f1b0000 0x801c>; |
132 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; | 134 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
133 | clocks = <&sdio4_clk>; | 135 | clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>; |
134 | status = "disabled"; | 136 | status = "disabled"; |
135 | }; | 137 | }; |
136 | 138 | ||
@@ -140,7 +142,7 @@ | |||
140 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; | 142 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
141 | #address-cells = <1>; | 143 | #address-cells = <1>; |
142 | #size-cells = <0>; | 144 | #size-cells = <0>; |
143 | clocks = <&bsc1_clk>; | 145 | clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>; |
144 | status = "disabled"; | 146 | status = "disabled"; |
145 | }; | 147 | }; |
146 | 148 | ||
@@ -150,7 +152,7 @@ | |||
150 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; | 152 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; |
151 | #address-cells = <1>; | 153 | #address-cells = <1>; |
152 | #size-cells = <0>; | 154 | #size-cells = <0>; |
153 | clocks = <&bsc2_clk>; | 155 | clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>; |
154 | status = "disabled"; | 156 | status = "disabled"; |
155 | }; | 157 | }; |
156 | 158 | ||
@@ -160,7 +162,7 @@ | |||
160 | interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; | 162 | interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; |
161 | #address-cells = <1>; | 163 | #address-cells = <1>; |
162 | #size-cells = <0>; | 164 | #size-cells = <0>; |
163 | clocks = <&bsc3_clk>; | 165 | clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>; |
164 | status = "disabled"; | 166 | status = "disabled"; |
165 | }; | 167 | }; |
166 | 168 | ||
@@ -170,105 +172,149 @@ | |||
170 | interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; | 172 | interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; |
171 | #address-cells = <1>; | 173 | #address-cells = <1>; |
172 | #size-cells = <0>; | 174 | #size-cells = <0>; |
173 | clocks = <&bsc4_clk>; | 175 | clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>; |
174 | status = "disabled"; | 176 | status = "disabled"; |
175 | }; | 177 | }; |
176 | 178 | ||
177 | clocks { | 179 | clocks { |
178 | bsc1_clk: bsc1 { | 180 | #address-cells = <1>; |
179 | compatible = "fixed-clock"; | 181 | #size-cells = <1>; |
180 | clock-frequency = <13000000>; | 182 | ranges; |
181 | #clock-cells = <0>; | ||
182 | }; | ||
183 | 183 | ||
184 | bsc2_clk: bsc2 { | 184 | /* |
185 | compatible = "fixed-clock"; | 185 | * Fixed clocks are defined before CCUs whose |
186 | clock-frequency = <13000000>; | 186 | * clocks may depend on them. |
187 | */ | ||
188 | |||
189 | ref_32k_clk: ref_32k { | ||
187 | #clock-cells = <0>; | 190 | #clock-cells = <0>; |
191 | compatible = "fixed-clock"; | ||
192 | clock-frequency = <32768>; | ||
188 | }; | 193 | }; |
189 | 194 | ||
190 | bsc3_clk: bsc3 { | 195 | bbl_32k_clk: bbl_32k { |
191 | compatible = "fixed-clock"; | ||
192 | clock-frequency = <13000000>; | ||
193 | #clock-cells = <0>; | 196 | #clock-cells = <0>; |
197 | compatible = "fixed-clock"; | ||
198 | clock-frequency = <32768>; | ||
194 | }; | 199 | }; |
195 | 200 | ||
196 | bsc4_clk: bsc4 { | 201 | ref_13m_clk: ref_13m { |
202 | #clock-cells = <0>; | ||
197 | compatible = "fixed-clock"; | 203 | compatible = "fixed-clock"; |
198 | clock-frequency = <13000000>; | 204 | clock-frequency = <13000000>; |
199 | #clock-cells = <0>; | ||
200 | }; | 205 | }; |
201 | 206 | ||
202 | pmu_bsc_clk: pmu_bsc { | 207 | var_13m_clk: var_13m { |
208 | #clock-cells = <0>; | ||
203 | compatible = "fixed-clock"; | 209 | compatible = "fixed-clock"; |
204 | clock-frequency = <13000000>; | 210 | clock-frequency = <13000000>; |
205 | #clock-cells = <0>; | ||
206 | }; | 211 | }; |
207 | 212 | ||
208 | hub_timer_clk: hub_timer { | 213 | dft_19_5m_clk: dft_19_5m { |
209 | compatible = "fixed-clock"; | ||
210 | clock-frequency = <32768>; | ||
211 | #clock-cells = <0>; | 214 | #clock-cells = <0>; |
215 | compatible = "fixed-clock"; | ||
216 | clock-frequency = <19500000>; | ||
212 | }; | 217 | }; |
213 | 218 | ||
214 | pwm_clk: pwm { | 219 | ref_crystal_clk: ref_crystal { |
220 | #clock-cells = <0>; | ||
215 | compatible = "fixed-clock"; | 221 | compatible = "fixed-clock"; |
216 | clock-frequency = <26000000>; | 222 | clock-frequency = <26000000>; |
217 | #clock-cells = <0>; | ||
218 | }; | 223 | }; |
219 | 224 | ||
220 | sdio1_clk: sdio1 { | 225 | ref_52m_clk: ref_52m { |
221 | compatible = "fixed-clock"; | ||
222 | clock-frequency = <48000000>; | ||
223 | #clock-cells = <0>; | 226 | #clock-cells = <0>; |
227 | compatible = "fixed-clock"; | ||
228 | clock-frequency = <52000000>; | ||
224 | }; | 229 | }; |
225 | 230 | ||
226 | sdio2_clk: sdio2 { | 231 | var_52m_clk: var_52m { |
227 | compatible = "fixed-clock"; | ||
228 | clock-frequency = <48000000>; | ||
229 | #clock-cells = <0>; | 232 | #clock-cells = <0>; |
233 | compatible = "fixed-clock"; | ||
234 | clock-frequency = <52000000>; | ||
230 | }; | 235 | }; |
231 | 236 | ||
232 | sdio3_clk: sdio3 { | 237 | usb_otg_ahb_clk: usb_otg_ahb { |
233 | compatible = "fixed-clock"; | ||
234 | clock-frequency = <48000000>; | ||
235 | #clock-cells = <0>; | 238 | #clock-cells = <0>; |
239 | compatible = "fixed-clock"; | ||
240 | clock-frequency = <52000000>; | ||
236 | }; | 241 | }; |
237 | 242 | ||
238 | sdio4_clk: sdio4 { | 243 | ref_96m_clk: ref_96m { |
239 | compatible = "fixed-clock"; | ||
240 | clock-frequency = <48000000>; | ||
241 | #clock-cells = <0>; | 244 | #clock-cells = <0>; |
245 | compatible = "fixed-clock"; | ||
246 | clock-frequency = <96000000>; | ||
242 | }; | 247 | }; |
243 | 248 | ||
244 | tmon_1m_clk: tmon_1m { | 249 | var_96m_clk: var_96m { |
245 | compatible = "fixed-clock"; | ||
246 | clock-frequency = <1000000>; | ||
247 | #clock-cells = <0>; | 250 | #clock-cells = <0>; |
251 | compatible = "fixed-clock"; | ||
252 | clock-frequency = <96000000>; | ||
248 | }; | 253 | }; |
249 | 254 | ||
250 | uartb_clk: uartb { | 255 | ref_104m_clk: ref_104m { |
251 | compatible = "fixed-clock"; | ||
252 | clock-frequency = <13000000>; | ||
253 | #clock-cells = <0>; | 256 | #clock-cells = <0>; |
257 | compatible = "fixed-clock"; | ||
258 | clock-frequency = <104000000>; | ||
254 | }; | 259 | }; |
255 | 260 | ||
256 | uartb2_clk: uartb2 { | 261 | var_104m_clk: var_104m { |
257 | compatible = "fixed-clock"; | ||
258 | clock-frequency = <13000000>; | ||
259 | #clock-cells = <0>; | 262 | #clock-cells = <0>; |
263 | compatible = "fixed-clock"; | ||
264 | clock-frequency = <104000000>; | ||
260 | }; | 265 | }; |
261 | 266 | ||
262 | uartb3_clk: uartb3 { | 267 | ref_156m_clk: ref_156m { |
263 | compatible = "fixed-clock"; | ||
264 | clock-frequency = <13000000>; | ||
265 | #clock-cells = <0>; | 268 | #clock-cells = <0>; |
269 | compatible = "fixed-clock"; | ||
270 | clock-frequency = <156000000>; | ||
266 | }; | 271 | }; |
267 | 272 | ||
268 | usb_otg_ahb_clk: usb_otg_ahb { | 273 | var_156m_clk: var_156m { |
269 | compatible = "fixed-clock"; | ||
270 | clock-frequency = <52000000>; | ||
271 | #clock-cells = <0>; | 274 | #clock-cells = <0>; |
275 | compatible = "fixed-clock"; | ||
276 | clock-frequency = <156000000>; | ||
277 | }; | ||
278 | |||
279 | root_ccu: root_ccu { | ||
280 | compatible = BCM21664_DT_ROOT_CCU_COMPAT; | ||
281 | reg = <0x35001000 0x0f00>; | ||
282 | #clock-cells = <1>; | ||
283 | clock-output-names = "frac_1m"; | ||
284 | }; | ||
285 | |||
286 | aon_ccu: aon_ccu { | ||
287 | compatible = BCM21664_DT_AON_CCU_COMPAT; | ||
288 | reg = <0x35002000 0x0f00>; | ||
289 | #clock-cells = <1>; | ||
290 | clock-output-names = "hub_timer"; | ||
291 | }; | ||
292 | |||
293 | master_ccu: master_ccu { | ||
294 | compatible = BCM21664_DT_MASTER_CCU_COMPAT; | ||
295 | reg = <0x3f001000 0x0f00>; | ||
296 | #clock-cells = <1>; | ||
297 | clock-output-names = "sdio1", | ||
298 | "sdio2", | ||
299 | "sdio3", | ||
300 | "sdio4", | ||
301 | "sdio1_sleep", | ||
302 | "sdio2_sleep", | ||
303 | "sdio3_sleep", | ||
304 | "sdio4_sleep"; | ||
305 | }; | ||
306 | |||
307 | slave_ccu: slave_ccu { | ||
308 | compatible = BCM21664_DT_SLAVE_CCU_COMPAT; | ||
309 | reg = <0x3e011000 0x0f00>; | ||
310 | #clock-cells = <1>; | ||
311 | clock-output-names = "uartb", | ||
312 | "uartb2", | ||
313 | "uartb3", | ||
314 | "bsc1", | ||
315 | "bsc2", | ||
316 | "bsc3", | ||
317 | "bsc4"; | ||
272 | }; | 318 | }; |
273 | }; | 319 | }; |
274 | 320 | ||