aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/boot
diff options
context:
space:
mode:
authorShawn Guo <shawn.guo@linaro.org>2013-02-04 10:09:16 -0500
committerShawn Guo <shawn.guo@linaro.org>2013-02-10 10:25:47 -0500
commit7c1da5854f3a4af7e44c059fdde750119c05f1a4 (patch)
treeaffe02e4032dec77f675336257b1761f9a2a1164 /arch/arm/boot
parent4bacf2a3fc07a89b4c0dca5a90e68eace9ea8813 (diff)
ARM: dts: add dtsi for imx6q and imx6dl
Add dtsi for imx6q and imx6dl with non-common blocks moved into there. Major differences between imx6dl and imx6q: * Dual vs. Quad cores * single vs. dual IPU * 128 vs. 256 KB OCRAM * imx6q: ECSPI5, OpenVG (GC355), SATA * imx6dl: I2C4, PXP, EPDC, LCDIF * iomuxc/pads definition Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/imx6dl.dtsi59
-rw-r--r--arch/arm/boot/dts/imx6q-arm2.dts2
-rw-r--r--arch/arm/boot/dts/imx6q-sabreauto.dts2
-rw-r--r--arch/arm/boot/dts/imx6q-sabrelite.dts2
-rw-r--r--arch/arm/boot/dts/imx6q-sabresd.dts2
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi296
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi277
7 files changed, 359 insertions, 281 deletions
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
new file mode 100644
index 000000000000..63fafe2a606c
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -0,0 +1,59 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10/include/ "imx6qdl.dtsi"
11
12/ {
13 cpus {
14 #address-cells = <1>;
15 #size-cells = <0>;
16
17 cpu@0 {
18 compatible = "arm,cortex-a9";
19 reg = <0>;
20 next-level-cache = <&L2>;
21 };
22
23 cpu@1 {
24 compatible = "arm,cortex-a9";
25 reg = <1>;
26 next-level-cache = <&L2>;
27 };
28 };
29
30 soc {
31 aips1: aips-bus@02000000 {
32 pxp: pxp@020f0000 {
33 reg = <0x020f0000 0x4000>;
34 interrupts = <0 98 0x04>;
35 };
36
37 epdc: epdc@020f4000 {
38 reg = <0x020f4000 0x4000>;
39 interrupts = <0 97 0x04>;
40 };
41
42 lcdif: lcdif@020f8000 {
43 reg = <0x020f8000 0x4000>;
44 interrupts = <0 39 0x04>;
45 };
46 };
47
48 aips2: aips-bus@02100000 {
49 i2c4: i2c@021f8000 {
50 #address-cells = <1>;
51 #size-cells = <0>;
52 compatible = "fsl,imx1-i2c";
53 reg = <0x021f8000 0x4000>;
54 interrupts = <0 35 0x04>;
55 status = "disabled";
56 };
57 };
58 };
59};
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index cd5813da1cee..53eb241fa5ad 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -11,7 +11,7 @@
11 */ 11 */
12 12
13/dts-v1/; 13/dts-v1/;
14/include/ "imx6qdl.dtsi" 14/include/ "imx6q.dtsi"
15 15
16/ { 16/ {
17 model = "Freescale i.MX6 Quad Armadillo2 Board"; 17 model = "Freescale i.MX6 Quad Armadillo2 Board";
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts
index 5baa82427f3f..656d489122fe 100644
--- a/arch/arm/boot/dts/imx6q-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
@@ -11,7 +11,7 @@
11 */ 11 */
12 12
13/dts-v1/; 13/dts-v1/;
14/include/ "imx6qdl.dtsi" 14/include/ "imx6q.dtsi"
15 15
16/ { 16/ {
17 model = "Freescale i.MX6 Quad SABRE Automotive Board"; 17 model = "Freescale i.MX6 Quad SABRE Automotive Board";
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 6aaaf69e88eb..2ce355cd05e5 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -11,7 +11,7 @@
11 */ 11 */
12 12
13/dts-v1/; 13/dts-v1/;
14/include/ "imx6qdl.dtsi" 14/include/ "imx6q.dtsi"
15 15
16/ { 16/ {
17 model = "Freescale i.MX6 Quad SABRE Lite Board"; 17 model = "Freescale i.MX6 Quad SABRE Lite Board";
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
index a48528f6f042..2dea304a7980 100644
--- a/arch/arm/boot/dts/imx6q-sabresd.dts
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
@@ -11,7 +11,7 @@
11 */ 11 */
12 12
13/dts-v1/; 13/dts-v1/;
14/include/ "imx6qdl.dtsi" 14/include/ "imx6q.dtsi"
15 15
16/ { 16/ {
17 model = "Freescale i.MX6Q SABRE Smart Device Board"; 17 model = "Freescale i.MX6Q SABRE Smart Device Board";
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
new file mode 100644
index 000000000000..cba021eb035e
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -0,0 +1,296 @@
1
2/*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 */
10
11/include/ "imx6qdl.dtsi"
12
13/ {
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu@0 {
19 compatible = "arm,cortex-a9";
20 reg = <0>;
21 next-level-cache = <&L2>;
22 operating-points = <
23 /* kHz uV */
24 1200000 1275000
25 996000 1250000
26 792000 1150000
27 396000 950000
28 >;
29 clock-latency = <61036>; /* two CLK32 periods */
30 clocks = <&clks 104>, <&clks 6>, <&clks 16>,
31 <&clks 17>, <&clks 170>;
32 clock-names = "arm", "pll2_pfd2_396m", "step",
33 "pll1_sw", "pll1_sys";
34 arm-supply = <&reg_arm>;
35 pu-supply = <&reg_pu>;
36 soc-supply = <&reg_soc>;
37 };
38
39 cpu@1 {
40 compatible = "arm,cortex-a9";
41 reg = <1>;
42 next-level-cache = <&L2>;
43 };
44
45 cpu@2 {
46 compatible = "arm,cortex-a9";
47 reg = <2>;
48 next-level-cache = <&L2>;
49 };
50
51 cpu@3 {
52 compatible = "arm,cortex-a9";
53 reg = <3>;
54 next-level-cache = <&L2>;
55 };
56 };
57
58 soc {
59 aips-bus@02000000 { /* AIPS1 */
60 spba-bus@02000000 {
61 ecspi5: ecspi@02018000 {
62 #address-cells = <1>;
63 #size-cells = <0>;
64 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
65 reg = <0x02018000 0x4000>;
66 interrupts = <0 35 0x04>;
67 clocks = <&clks 116>, <&clks 116>;
68 clock-names = "ipg", "per";
69 status = "disabled";
70 };
71 };
72
73 iomuxc: iomuxc@020e0000 {
74 compatible = "fsl,imx6q-iomuxc";
75 reg = <0x020e0000 0x4000>;
76
77 /* shared pinctrl settings */
78 audmux {
79 pinctrl_audmux_1: audmux-1 {
80 fsl,pins = <
81 18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
82 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
83 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
84 3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
85 >;
86 };
87 };
88
89 ecspi1 {
90 pinctrl_ecspi1_1: ecspi1grp-1 {
91 fsl,pins = <
92 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
93 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
94 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
95 >;
96 };
97 };
98
99 enet {
100 pinctrl_enet_1: enetgrp-1 {
101 fsl,pins = <
102 695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
103 756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */
104 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
105 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
106 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
107 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
108 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
109 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
110 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
111 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
112 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
113 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
114 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
115 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
116 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
117 1033 0x4001b0a8 /* MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT*/
118 >;
119 };
120
121 pinctrl_enet_2: enetgrp-2 {
122 fsl,pins = <
123 890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
124 909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */
125 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
126 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
127 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
128 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
129 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
130 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
131 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
132 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
133 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
134 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
135 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
136 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
137 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
138 >;
139 };
140 };
141
142 gpmi-nand {
143 pinctrl_gpmi_nand_1: gpmi-nand-1 {
144 fsl,pins = <
145 1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
146 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
147 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
148 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
149 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
150 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
151 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
152 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
153 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
154 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
155 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
156 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
157 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
158 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
159 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
160 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
161 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
162 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
163 1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
164 >;
165 };
166 };
167
168 i2c1 {
169 pinctrl_i2c1_1: i2c1grp-1 {
170 fsl,pins = <
171 137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
172 196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */
173 >;
174 };
175 };
176
177 uart1 {
178 pinctrl_uart1_1: uart1grp-1 {
179 fsl,pins = <
180 1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
181 1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
182 >;
183 };
184 };
185
186 uart2 {
187 pinctrl_uart2_1: uart2grp-1 {
188 fsl,pins = <
189 183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
190 191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */
191 >;
192 };
193 };
194
195 uart4 {
196 pinctrl_uart4_1: uart4grp-1 {
197 fsl,pins = <
198 877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */
199 885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
200 >;
201 };
202 };
203
204 usbotg {
205 pinctrl_usbotg_1: usbotggrp-1 {
206 fsl,pins = <
207 1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */
208 >;
209 };
210 };
211
212 usdhc2 {
213 pinctrl_usdhc2_1: usdhc2grp-1 {
214 fsl,pins = <
215 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
216 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
217 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
218 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
219 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
220 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
221 1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
222 1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
223 1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
224 1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
225 >;
226 };
227 };
228
229 usdhc3 {
230 pinctrl_usdhc3_1: usdhc3grp-1 {
231 fsl,pins = <
232 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
233 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
234 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
235 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
236 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
237 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
238 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
239 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
240 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
241 1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
242 >;
243 };
244
245 pinctrl_usdhc3_2: usdhc3grp-2 {
246 fsl,pins = <
247 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
248 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
249 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
250 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
251 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
252 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
253 >;
254 };
255 };
256
257 usdhc4 {
258 pinctrl_usdhc4_1: usdhc4grp-1 {
259 fsl,pins = <
260 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
261 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
262 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
263 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
264 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
265 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
266 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
267 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
268 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
269 1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
270 >;
271 };
272
273 pinctrl_usdhc4_2: usdhc4grp-2 {
274 fsl,pins = <
275 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
276 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
277 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
278 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
279 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
280 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
281 >;
282 };
283 };
284 };
285 };
286
287 ipu2: ipu@02800000 {
288 #crtc-cells = <1>;
289 compatible = "fsl,imx6q-ipu";
290 reg = <0x02800000 0x400000>;
291 interrupts = <0 8 0x4 0 7 0x4>;
292 clocks = <&clks 133>, <&clks 134>, <&clks 137>;
293 clock-names = "bus", "di0", "di1";
294 };
295 };
296};
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index ad10d82c6160..06ec460b4581 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -28,50 +28,6 @@
28 gpio6 = &gpio7; 28 gpio6 = &gpio7;
29 }; 29 };
30 30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu@0 {
36 compatible = "arm,cortex-a9";
37 reg = <0>;
38 next-level-cache = <&L2>;
39 operating-points = <
40 /* kHz uV */
41 1200000 1275000
42 996000 1250000
43 792000 1150000
44 396000 950000
45 >;
46 clock-latency = <61036>; /* two CLK32 periods */
47 clocks = <&clks 104>, <&clks 6>, <&clks 16>,
48 <&clks 17>, <&clks 170>;
49 clock-names = "arm", "pll2_pfd2_396m", "step",
50 "pll1_sw", "pll1_sys";
51 arm-supply = <&reg_arm>;
52 pu-supply = <&reg_pu>;
53 soc-supply = <&reg_soc>;
54 };
55
56 cpu@1 {
57 compatible = "arm,cortex-a9";
58 reg = <1>;
59 next-level-cache = <&L2>;
60 };
61
62 cpu@2 {
63 compatible = "arm,cortex-a9";
64 reg = <2>;
65 next-level-cache = <&L2>;
66 };
67
68 cpu@3 {
69 compatible = "arm,cortex-a9";
70 reg = <3>;
71 next-level-cache = <&L2>;
72 };
73 };
74
75 intc: interrupt-controller@00a01000 { 31 intc: interrupt-controller@00a01000 {
76 compatible = "arm,cortex-a9-gic"; 32 compatible = "arm,cortex-a9-gic";
77 #interrupt-cells = <3>; 33 #interrupt-cells = <3>;
@@ -208,17 +164,6 @@
208 status = "disabled"; 164 status = "disabled";
209 }; 165 };
210 166
211 ecspi5: ecspi@02018000 {
212 #address-cells = <1>;
213 #size-cells = <0>;
214 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
215 reg = <0x02018000 0x4000>;
216 interrupts = <0 35 0x04>;
217 clocks = <&clks 116>, <&clks 116>;
218 clock-names = "ipg", "per";
219 status = "disabled";
220 };
221
222 uart1: serial@02020000 { 167 uart1: serial@02020000 {
223 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 168 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
224 reg = <0x02020000 0x4000>; 169 reg = <0x02020000 0x4000>;
@@ -584,219 +529,6 @@
584 reg = <0x020e0000 0x38>; 529 reg = <0x020e0000 0x38>;
585 }; 530 };
586 531
587 iomuxc: iomuxc@020e0000 {
588 compatible = "fsl,imx6q-iomuxc";
589 reg = <0x020e0000 0x4000>;
590
591 /* shared pinctrl settings */
592 audmux {
593 pinctrl_audmux_1: audmux-1 {
594 fsl,pins = <
595 18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
596 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
597 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
598 3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
599 >;
600 };
601 };
602
603 ecspi1 {
604 pinctrl_ecspi1_1: ecspi1grp-1 {
605 fsl,pins = <
606 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
607 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
608 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
609 >;
610 };
611 };
612
613 enet {
614 pinctrl_enet_1: enetgrp-1 {
615 fsl,pins = <
616 695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
617 756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */
618 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
619 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
620 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
621 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
622 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
623 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
624 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
625 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
626 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
627 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
628 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
629 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
630 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
631 1033 0x4001b0a8 /* MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT*/
632 >;
633 };
634
635 pinctrl_enet_2: enetgrp-2 {
636 fsl,pins = <
637 890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
638 909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */
639 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
640 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
641 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
642 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
643 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
644 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
645 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
646 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
647 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
648 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
649 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
650 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
651 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
652 >;
653 };
654 };
655
656 gpmi-nand {
657 pinctrl_gpmi_nand_1: gpmi-nand-1 {
658 fsl,pins = <
659 1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
660 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
661 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
662 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
663 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
664 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
665 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
666 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
667 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
668 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
669 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
670 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
671 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
672 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
673 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
674 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
675 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
676 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
677 1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
678 >;
679 };
680 };
681
682 i2c1 {
683 pinctrl_i2c1_1: i2c1grp-1 {
684 fsl,pins = <
685 137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
686 196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */
687 >;
688 };
689 };
690
691 uart1 {
692 pinctrl_uart1_1: uart1grp-1 {
693 fsl,pins = <
694 1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
695 1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
696 >;
697 };
698 };
699
700 uart2 {
701 pinctrl_uart2_1: uart2grp-1 {
702 fsl,pins = <
703 183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
704 191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */
705 >;
706 };
707 };
708
709 uart4 {
710 pinctrl_uart4_1: uart4grp-1 {
711 fsl,pins = <
712 877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */
713 885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
714 >;
715 };
716 };
717
718 usbotg {
719 pinctrl_usbotg_1: usbotggrp-1 {
720 fsl,pins = <
721 1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */
722 >;
723 };
724 };
725
726 usdhc2 {
727 pinctrl_usdhc2_1: usdhc2grp-1 {
728 fsl,pins = <
729 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
730 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
731 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
732 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
733 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
734 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
735 1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
736 1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
737 1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
738 1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
739 >;
740 };
741 };
742
743 usdhc3 {
744 pinctrl_usdhc3_1: usdhc3grp-1 {
745 fsl,pins = <
746 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
747 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
748 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
749 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
750 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
751 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
752 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
753 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
754 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
755 1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
756 >;
757 };
758
759 pinctrl_usdhc3_2: usdhc3grp-2 {
760 fsl,pins = <
761 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
762 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
763 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
764 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
765 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
766 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
767 >;
768 };
769 };
770
771 usdhc4 {
772 pinctrl_usdhc4_1: usdhc4grp-1 {
773 fsl,pins = <
774 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
775 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
776 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
777 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
778 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
779 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
780 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
781 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
782 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
783 1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
784 >;
785 };
786
787 pinctrl_usdhc4_2: usdhc4grp-2 {
788 fsl,pins = <
789 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
790 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
791 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
792 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
793 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
794 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
795 >;
796 };
797 };
798 };
799
800 dcic1: dcic@020e4000 { 532 dcic1: dcic@020e4000 {
801 reg = <0x020e4000 0x4000>; 533 reg = <0x020e4000 0x4000>;
802 interrupts = <0 124 0x04>; 534 interrupts = <0 124 0x04>;
@@ -1064,14 +796,5 @@
1064 clocks = <&clks 130>, <&clks 131>, <&clks 132>; 796 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
1065 clock-names = "bus", "di0", "di1"; 797 clock-names = "bus", "di0", "di1";
1066 }; 798 };
1067
1068 ipu2: ipu@02800000 {
1069 #crtc-cells = <1>;
1070 compatible = "fsl,imx6q-ipu";
1071 reg = <0x02800000 0x400000>;
1072 interrupts = <0 8 0x4 0 7 0x4>;
1073 clocks = <&clks 133>, <&clks 134>, <&clks 137>;
1074 clock-names = "bus", "di0", "di1";
1075 };
1076 }; 799 };
1077}; 800};
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-01 17:14:01 -0500